cs5317 Cirrus Logic, Inc., cs5317 Datasheet
cs5317
Available stocks
Related parts for cs5317
cs5317 Summary of contents
Page 1
... P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com Description The CS5317 is an ideal analog front-end for voiceband signal processing applications such as high-perfor- mance modems, passive sonar, and voice recognition systems. It includes a 16-bit A/D converter with an inter- nal track & ...
Page 2
... Notes: 1. Measured over the full 0 to 9.6kHz band with a -20dB input and extrapolated to full-scale. Since this includes energy in the stopband above 5kHz, additional post-filtering at the CS5317’s output can typically achieve 88dB dynamic range by improving rejection above 5kHz. This can be increased to 90dB by bandlimiting the output to 2 ...
Page 3
... MIN MAX Symbol Min V 2 (Note 9) V (VD+)-1. out (DGND, AGND = 0V, see Note 10.) Symbol Min VD+ 4.5 VD- -4.5 VA+ 4.5 VA- -4.5 f 0.01 clk CS5317 Typ Max Units °C -10 -30 Mrad/Vs - 5.12 MHz -8 -12 A/rad 50 100 ns Typ Max Units - - ...
Page 4
... AGND = 0V, all voltages with repect to groung) Symbol VD+ VD- VA+ VA- (Note 13 (VA-) - 0.3 INA V IND stg CS5317 Typ Max Units - - 20 kHz - - 10 kHz - - 5.12 MHz - - 20 kHz - 20 1000 1000 ...
Page 5
... RST must be held high except in the clock override (CLKOR) mode where it can be used to align the phases of all internal clocks. DS27F4 t fallin 2.0 V 0.8 V Rise and Fall Times t pwh1 CLKIN Timing t phl2 t plh2 plh4 (MSB) Serial Output Timing t plh6 t su1 Reset Timing CS5317 t riseout t fallout t pwl1 t plh3 t plh1 plh5 t su1 t su2 t pwr 2 ...
Page 6
... On-chip digital filtering, an integral part of the delta-sigma ADC, processes the data and updates the 16-bit output register kHz. The CS5317 can be read at any rate kHz. The CS5317 is a CS5316 with an on-chip sam- pling clock generator. As such, it replaces the CS5316 and should be considered for all new de- signs ...
Page 7
... Some systems such as echo-canceling modems, though, require the output sampling rate to be locked to a sampling signal which is 20 kHz or below. For this reason the CS5317 includes an on-chip phase-lock loop (PLL) which can gener- ate its requisite 5.12 MHz master clock from a 20 kHz sampling signal. ...
Page 8
... Crystal Semiconductor recommends the CS5501, a low-cost, d.c. accurate, delta-sigma ADC featuring excellent 60 Hz rejection and a system-level calibration capability. The Analog Input Range and Coding Format The input range of the CS5317 is nominally with /256. clkin this gain error, analog input levels should be kept below pears MSB-first in 2’ ...
Page 9
... The digital filter then processes the input signal at the input sample rate. Like any sampled-data filter, though, the digital filter’s passband spectrum repeats around integer multiples of the sample rate, f the CS5317 is operating at its full-rated speed any j Mag H(e ) (dB) -2.74 dB ...
Page 10
... If the input signal contains a large amount of out- of-band energy, additional analog and/or digital antialias filtering may be required. If digital post- filtering is used to augment the CS5317’s rejection above f /4 (that is, above 5 kHz), the s out ...
Page 11
... A 3-state capability is available for bus-oriented applications. The 3-state control input is termed Data Output Enable, DOE, and is asynchronous with respect to the rest of the CS5317. If DOE is taken high at any time, even during a data burst, the DATA, DOUT and CLKOUT pins high impedance state. Any data which would be output while DOE is high is lost ...
Page 12
... Ko VCO [Ko is typ. -10Mrad/Vs.] vco in Counter/Divider Ratio The CS5317 PLL multiplies the CLKIN rate by an integer value. To set the multiplication rate, a counter/divider chain is used to divide the VCO output frequency to develop a clock whose fre- quency is compared to the CLKIN frequency in the phase detector. The binary counter/divider ra- ...
Page 13
... A current sources will saturate to the supplies and yield the following gain factor log 0.5 = 0.6 = 0 Figure 6b. Second Order PLL Frequency Response KoKd KoKd 0 0 CS5317 = ...
Page 14
... The CS5317 A/D sampling clock derived from a 9600 Hz clock source. The application requires the sig- nal passband of the CS5317 kHz. The on-chip digital filter of the CS5317 has passband of CLKOUT/488.65 (see Note 4 in the data sheet specifications tables). The 4 kHz pass- ...
Page 15
... The Blackman-Harris window used to test the CS5317 has a maximum side-lobe level of -92 dB. Figure 7 shows an FFT plot of a typical CS5317 with a 1 kHz sinewave input generated by an "ul- tra-pure" sine wave generator and the output multiplied by a Blackman-Harris window. Arti- ...
Page 16
... Full Scale -100dB -120dB dc Figure 8. CS5317 Intermodulation Distortion The plot below illustrates the typical DNL per- formance of the CS5317, and clearly shows the part easily achieves no missing codes. Schematic & Layout Review Service Confirm Optimum Confirm Optimum Schematic & Layout Schematic & Layout Before Building Your Board ...
Page 17
... DATA 7 VA- 14 MODE 8 REFBUF POSITIVE REFERENCE BUFFER 13 9 DOUT 12 AIN 10 CLKIN 11 VD- CS5317 VCO INPUT PHASE DETECT RESET ANALOG GROUND NEGATIVE ANALOG POWER NO CONNECT ANALOG INPUT NEGATIVE DIGITAL POWER VCO INPUT PHASE DETECT RESET ANALOG GROUND NO CONNECT NO CONNECT NEGATIVE ANALOG POWER ...
Page 18
... Sets phase of CLKOUT. Functions only in the clock override mode, CLKOR. Used to synchronize the output samples of multiple CS5317’s. Must be kept high in CLKG1 or CLKG2 modes. Also, tying this pin low, with MODE not tied to - 5V, will place the CS5317 into CSZ5316 compatible mode. ...
Page 19
... Bipolar Offset Drift - The drift in the bipolar offset error with temperature. Absolute Group Delay - The delay through the filter section of the part. Passband Frequency - The upper -3 dB frequency of the CS5317. DS27F4 CS5317 N ...
Page 20
... ORDERING GUIDE Model Number CS5317-KP CS5317-KS 20 Temperature Range CS5317 Package 18 Pin Plastic DIP 20 Pin Plastic SOIC DS27F4 ...
Page 21
... APPLICATIONS CS5317 DATA CLKOUT DOUT Only needed for level sensitive interrupt driven systems. CLKOUT DOUT DATA INT DS27F4 Figure A1 shows one method of converting the serial output of the CS5317 into 16-bit, parallel words. The associated timing is also shown. +5V OE2 ...
Page 22
... Figure A2 shows the interconnection and timing details for connecting a CS5317 to a NEC PD7730 DSP chip. Status Register (SR) Bit Mnemonic Setting 9 SCI SDLI SIF 0 CLKOUT DOUT DATA (MSB) Figure A2. CS5317-to-NEC PD77230 Serial Interface SSI Control Reg. A PINS CRA (X:FFEC) ...
Page 23
... Figure A4 shows the interconnection and timing details for connecting a CS5317 DSP16 DSP chip. Serial I/O Control Register (SIOC) Field Value Meaning MSB 1 MSB input first ILD 0 ILD is an input ICK 0 ICK is an input ILEN 0 16 bit input data CLKOUT DOUT DATA d ...
Page 24
Notes • ...
Page 25
... FAX: (512) 445 7581 http://www.crystal.com Description The CDB5317 Evaluation Board is designed to allow the user to quickly evaluate performance of the CS5317 Del- ta-Sigma Analog-to-Digital Converter. All that is required to use this board is an external power supply, a signal source, a clock source, and an ability to read either serial or parallel 16bitdata words ...
Page 26
... The signal to total harmonic distortion value for a particular input is the ratio of the RMS value of the input signal and the sum of the RMS values of the harmonics shown in the diagram. The dynamic range of the CS5317 can be measured by reducing the input 0dB -20dB -40dB -60dB ...
Page 27
... More complex analysis such as intermodulation distortion measurements can be accomplished with the addition of another sine-wave generator. CIRCUIT DESCRIPTION Figure 2 illustrates the CS5317 A/D converter IC circuit connections. The chip operates off of 5V. These voltages are supplied from a power source external to the evaluation board. Binding posts ...
Page 28
... CS5317 chip. The mode selection works together with the CLKIN signal to set the sample rate and the output word rate of the CS5317. See the CS5317 data sheet for details on mode selection. Two of the avail- able modes (CLKG1 and CLKG2) utilize the ...
Page 29
... DOUT Note: For a complete description of serial timing see the CS5317 Data Sheet two modes which use the phase locked loop will require appropriate low pass filter components on the Evaluation Board. The low pass filter compo- nents help determine the PLL control loop ...
Page 30
... DOUT signal from the CS5317 is used to latch the data once it is input to the shift registers. The rising edge of DOUT is also used to toggle the DRDY flip flop (see Figure 3). The flip flop is used to signal a remote device whenever new CLKIN (fig. 2) CLKOUT2 (fig ...
Page 31
DS27DB3 Figure 7. Bird’s Eye View CDB5317 31 ...
Page 32
...