adc08d1000wgfqv National Semiconductor Corporation, adc08d1000wgfqv Datasheet
adc08d1000wgfqv
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adc08d1000wgfqv Summary of contents
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... Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Indus- trial (-40˚C ≤ T ≤ +85˚C) temperature range. A Block Diagram © 2005 National Semiconductor Corporation Features n Internal Sample-and-Hold n Single +1.9V n Choice of SDR or DDR output clocking n Interleave Mode for 2x Sampling Rate ...
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Ordering Information Industrial Temperature Range (-40˚ ADC08D1000CIYB ADC08D1000EVAL Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com < < +85˚C) 128-Pin Exposed Pad LQFP 2 NS Package ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit 3 OutV / SCLK OutEdge / DDR 4 / SDATA 15 DCLK_RST PDQ 30 CAL 14 FSR/ECE CalDly / DES / 127 SCS Description Output ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 18 CLK+ 19 CLK I− Q− CMO 126 CalRun ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 40, 51 ,62, 73 88, 99, 110, 121 12, 21, GND 24, 27, 41 42, 53, 64, 74, DR GND 87, 97, 108, 119 52, ...
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Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Input Pin Ground Difference |GND ...
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Converter Electrical Characteristics The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Floating, Non-Extended Control Mode, SDR Mode, R tial. Boldface limits apply for T = ...
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Converter Electrical Characteristics The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Floating, Non-Extended Control Mode, SDR Mode, R tial. Boldface limits apply for T = ...
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Converter Electrical Characteristics The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Floating, Non-Extended Control Mode, SDR Mode, R tial. Boldface limits apply for T = ...
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Converter Electrical Characteristics The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Floating, Non-Extended Control Mode, SDR Mode, R tial. Boldface limits apply for T = ...
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Converter Electrical Characteristics The following specifications apply after calibration for V 870mV , pF, Differential, a.c. coupled Sinewave Input Clock, f P-P L Floating, Non-Extended Control Mode, SDR Mode, R tial. Boldface limits apply for T = ...
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Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode the aperture ...
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Specification Definitions SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of the sum of all other spectral components below one-half the sampling ...
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Timing Diagrams FIGURE 3. ADC08D1000 Timing — SDR Clocking FIGURE 4. ADC08D1000 Timing — DDR Clocking 15 20097414 20097459 www.national.com ...
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Timing Diagrams (Continued) FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low www.national.com FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode 16 20097419 20097420 20097423 ...
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Timing Diagrams (Continued) FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing 17 20097424 20097425 www.national.com ...
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Typical Performance Characteristics stated. INL vs CODE DNL vs. CODE POWER DISSIPATION vs. SAMPLE RATE www.national.com V =V =1.9V, F =1000MHz CLK INL vs TEMPERATURE 20097464 DNL vs. TEMPERATURE 20097466 ENOB vs. CLOCK DUTY CYCLE 20097481 18 ...
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Typical Performance Characteristics stated. (Continued) ENOB vs. TEMPERATURE ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE V =V =1.9V, F =1000MHz CLK ENOB vs. SUPPLY VOLTAGE 20097476 ENOB vs. INPUT FREQUENCY 20097478 SNR vs. SUPPLY VOLTAGE 20097468 19 ...
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Typical Performance Characteristics stated. (Continued) SNR vs. SAMPLE RATE THD vs. TEMPERATURE THD vs. SAMPLE RATE www.national.com V =V =1.9V, F =1000MHz CLK SNR vs. INPUT FREQUENCY 20097470 THD vs. SUPPLY VOLTAGE 20097472 THD vs. INPUT FREQUENCY ...
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Typical Performance Characteristics stated. (Continued) SFDR vs. TEMPERATURE SFDR vs. SAMPLE RATE Spectral Response at FIN = 248 MHZ V =V =1.9V, F =1000MHz CLK SFDR vs. SUPPLY VOLTAGE 20097485 SFDR vs. INPUT FREQUENCY 20097482 Spectral Response ...
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Typical Performance Characteristics stated. (Continued) CROSSTALK vs SOURCE FREQUENCY STEP RESPONSE www.national.com V =V =1.9V, F =1000MHz CLK FULL POWER BANDWIDTH 20097463 STEP RESPONSE DETAIL VIEW 20097461 22 =25˚C unless otherwise A 20097486 20097462 ...
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Functional Description The ADC08D1000 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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Functional Description controls are disabled. These pins are OutV (pin 3), OutEdge/ DDR (pin 4), FSR (pin 14) and CalDly/DES (pin 127). See Section 1.2 for details on the Extended Control mode. 1.1.4 The Analog Inputs The ADC08D1000 must ...
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Functional Description 1.1.6 The LVDS Outputs The data outputs, the Out Of Range (OR) and DCLK, are LVDS. Output current sources provide output current to a differential 100 Ohm load when the OutV input (pin 14) ...
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Functional Description The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device) and is shown in Table 3. TABLE 3. Extended Control Mode Operation (Pin 14 Floating) Extended Control Mode Feature ...
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Functional Description Bit 11 DCP: DDR Clock Phase. This bit only has an effect in the DDR mode. When this bit is set to 0b, the DCLK edges are time-aligned with the data bus edges ("0˚ Phase"). When this ...
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Functional Description Q-Channel Full-Scale Voltage Adjust Addr: Bh (1011b) D15 D14 D13 D12 D11 (MSB) Adjust Value (LSB Bit 15:7 Full Scale Voltage Adjust Value. The input full-scale voltage or ...
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Functional Description DES Fine Adjust Addr: Fh (1111b) D15 D14 D13 D12 D11 D10 (MSB) FAM (LSB Bits 15:7 Fine Adjust Magnitude. Each code value in this field delays either ...
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Applications Information (Continued) reduced to 75% of the values indicated. In the Enhanced Control Mode, these values will be determined by the full scale range and offset settings in the Control Registers. TABLE 5. DIFFERENTIAL INPUT TO OUTPUT RELATIONSHIP ...
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Applications Information (Continued) 2.2.1 Handling Single-Ended Input Signals There is no provision for the ADC08D1000 to adequately process single-ended input signals. The best way to handle single-ended signals is to convert them to differential signals before presenting them to ...
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Applications Information (Continued) Input clock amplitudes above those specified in the Electrical Characteristics Table may result in increased input offset voltage. This would cause the converter to produce an out- put code other than the expected 127/128 when both ...
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Applications Information (Continued) FIGURE 16. ENOB vs. Junction Temperature, 249MHz input 2.4.2.3 Calibration Delay The CalDly input (pin 127) is used to select one of two delay times after the application of power to the start of calibration, as ...
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Applications Information (Continued) sequence until the PD input goes low manual calibration is requested while the device is powered down, the calibra- tion will not begin at all. That is, the manual calibration input is completely ignored ...
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Applications Information (Continued) exceed 130˚C. This is not a problem if the ambient tempera- ture is kept to a maximum of +85˚C as specified in the Operating Ratings section. Please note that the following are general recommendations for mounting ...
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Applications Information (Continued) CLK input must exhibit low rms jitter. The allowable jitter is a function of the input frequency and the input signal level, as described in Section 2. good practice to keep the ADC input ...
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Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right ...