ad1859jrz Analog Devices, Inc., ad1859jrz Datasheet

ad1859jrz

Manufacturer Part Number

ad1859jrz

Description

Stereo, Single-supply 18-bit Integrated Dac

Manufacturer

Analog Devices, Inc.

Datasheet

1.AD1859JRZ.pdf (16 pages)

Available stocks

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Part Number

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Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

AD1859JRZ

Manufacturer:

ADI/亚德诺

Quantity:

20 000

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*SPI is a registered trademark of Motorola, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

FEATURES

Complete, Low Cost Stereo DAC System in a Single Die

Variable Rate Oversampling Interpolation Filter

Multibit

Discrete and Continuous Time Analog Reconstruction

Extremely Low Out-of-Band Energy

64 Step (1 dB/Step) Analog Attenuator with Mute

Buffered Outputs with 2 k

Rejects Sample Clock Jitter

94 dB Dynamic Range, –88 dB THD+N Performance

Option for Analog De-emphasis Processing with

Continuously Variable Sample Rate Support

Digital Phase Locked Loop Based Asynchronous Master

On-Chip Master Clock Oscillator, Only External Crystal

Power-Down Mode

Flexible Serial Data Port (I

SPI* Compatible Serial Control Port

Single +5 V Supply

28-Pin SOIC and SSOP Packages

APPLICATIONS

Digital Cable TV and Direct Broadcast Satellite Set-Top

Digital Video Disc, Video CD and CD-I Players

High Definition Televisions, Digital Audio Broadcast

CD, CD-R, DAT, DCC, ATAPI CD-ROM and MD Players

Digital Audio Workstations, Computer Multimedia

0.1 Maximum Phase Linearity Deviation

Filters

External Passive Components

Is Required

Right-Justified and DSP Serial Port Modes)

Decoder Boxes

Receivers

Products

Package

Clock

Modulator with Triangular PDF Dither

DIGITAL DATA

16- OR 18-BIT

INPUT

S-Justified, Left-Justified,

Output Load Drive

INTERFACE

SERIAL

DATA

AD1859

VARIABLE RATE

INTERPOLATION

VARIABLE RATE

INTERPOLATION

DOWN/RESET

POWER

FUNCTIONAL BLOCK DIAGRAM

DIGITAL

SUPPLY

CONTROL

INTERFACE

CONTROL

MUTE

MODULATOR

MULTIBIT

MODULATOR

MULTIBIT

INPUT

SERIAL

DATA

DE-EMPHASIS

PRODUCT OVERVIEW

The AD1859 is a complete 16-/18-bit single-chip stereo digital

audio playback subsystem. It comprises a variable rate digital

interpolation filter, a revolutionary multibit sigma-delta (

modulator with dither, a jitter-tolerant DAC, switched capacitor

and continuous time analog filters, and analog output drive cir-

cuitry. Other features include an on-chip stereo attenuator and

mute, programmed through an SPI-compatible serial control

port.

The key differentiating feature of the AD1859 is its asynchro-

nous master clock capability. Previous

quired a high frequency master clock at 256 or 384 times the

intended audio sample rate. The generation and management

of this high frequency synchronous clock is burdensome to the

board level designer. The analog performance of conventional

single bit

the sample and master clocks. The AD1859 has a digital Phase

Locked Loop (PLL) which allows the master clock to be asyn-

chronous, and which also strongly rejects jitter on the sample

clock (left/right clock). The digital PLL allows the AD1859 to

can vary over a wide range. The digital PLL will lock to the

new sample rate in approximately 100 ms. Jitter components

15 Hz above and below the sample frequency are rejected by

6 dB per octave. This level of jitter rejection is unprecedented

in audio DACs.

The AD1859 supports continuously variable sample rates with

essentially linear phase response, and with an option for external

analog de-emphasis processing. The clock circuit includes an

on-chip oscillator, so that the user need only provide an external

crystal. The oscillator may be overdriven, if desired, with an ex-

ternal clock source.

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700

be clocked with a single frequency (27 MHz for example) while

the sample frequency (as determined from the left/right clock)

REFERENCE

FILTER AND

VOLTAGE

GROUND

DAC

ANALOG

FILTER

18-Bit Integrated

DACs is also dependent on the spectral purity of

ATTEN/

MUTE

ASYNCHRONOUS

CLOCK/CRYSTAL

Stereo, Single-Supply

DPLL/CLOCK

MANAGER

ANALOG

SUPPLY

OUTPUT

BUFFER

OUTPUT

BUFFER

DE-EMPHASIS

SWITCH LEFT

COMMON MODE

DE-EMPHASIS

SWITCH RIGHT

ANALOG

OUTPUTS

audio DACs re-

(continued on page 7)

AD1859

Fax: 617/326-8703

DAC

)

Related parts for ad1859jrz

ad1859jrz Summary of contents

Page 1

... ASYNCHRONOUS CLOCK/CRYSTAL 2 DPLL/CLOCK DE-EMPHASIS MANAGER SWITCH LEFT COMMON MODE ANALOG ATTEN/ OUTPUT FILTER MUTE BUFFER ANALOG OUTPUTS ANALOG ATTEN/ OUTPUT FILTER MUTE BUFFER DE-EMPHASIS SWITCH RIGHT 2 ANALOG SUPPLY © Analog Devices, Inc., 1996 DAC AD1859 ) audio DACs re- (continued on page 7) Fax: 617/326-8703 ...

Page 2

AD1859–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages ( Ambient Temperature Input Clock (F ) MCLK Input Signal Input Sample Rate Measurement Bandwidth Input Data Word Width Load Capacitance Input Voltage ...

Page 3

DIGITAL TIMING (Guaranteed over – +105 BCLK HI Pulse Width DBH t BCLK LO Pulse Width DBL t BCLK Period DBP t LRCLK Setup DLS t LRCLK Hold (DSP Serial Port Style Mode Only) DLH ...

Page 4

AD1859 ABSOLUTE MAXIMUM RATINGS DGND AGND DD Digital Inputs Analog Inputs AGND to DGND Reference Voltage Soldering *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is ...

Page 5

DEFINITIONS Dynamic Range The ratio of a full-scale output signal to the integrated output noise in the passband ( kHz), expressed in decibels (dB). Dynamic range is measured with a –60 dB input signal and is equal to ...

Page 6

AD1859 Analog Signals Pin Name Number I/O Description FILT 28 O Voltage reference filter capacitor connection. Bypass and decouple the voltage reference with paral- lel 10 F and 0.1 F capacitors to the FGND pin. FGND 27 I Voltage reference ...

Page 7

The AD1859 has a simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. The serial data input port can ...

Page 8

AD1859 Option for Analog De-emphasis Processing The AD1859 includes three pins for implementing an external analog 50/15 s (or possibly the CCITT J. 17) de-emphasis fre- quency response characteristic. A control pin DEEMP (Pin 2) enables de-emphasis when it is ...

Page 9

Figure 3 shows the I S-justified mode. LRCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition but with ...

Page 10

AD1859 CCLK CDATA D7 D6 MSB CLATCH MSB DATA7 LEFT/RIGHT Right Channel = HI Mute = HI Left Channel = LO Normal = LO The serial control port is byte oriented. The data is MSB first, and is unsigned. There ...

Page 11

AD1859 has been designed to minimize pops and clicks when muting and unmuting the device. The AD1859 includes a zero crossing detector which attempts to implement attenuation changes on waveform zero crossings only zero crossing is not found ...

Page 12

AD1859 Figure 15 shows the suggested interface to the Zoran ZR38000 DSP chip, which can act as an MPEG audio or AC-3 audio decoder. The ZR38000 supports 16 bits of data using a left- justified output format. SCKB ZORAN WSB ...

Page 13

PCB and Ground Plane Recommendations The AD1859 ideally should be located above a split ground plane, with the digital pins over the digital ground plane, and the analog pins over the analog ground plane. The split should occur between Pins ...

Page 14

AD1859 TYPICAL PERFORMANCE Figures 24 through 27 illustrate the typical analog performance of the AD1859 as measured by an Audio Precision System One. Signal-to-Noise (dynamic range) and THD+N performance is shown under a range of conditions. Note that there is ...

Page 15

FREQUENCY – Hz Figure 30. 1 kHz Tone at –90 dBFS (16K-Point FFT) ...

Page 16

AD1859 13 N [12.. [12..0] 13-BIT ADDER 13 + Figure 33. Numerically Controlled Oscillator Circuit 28-Lead Wide-Body SO (R-28) 0.7125 (18.10) 0.6969 (17.70 0.1043 (2.65) PIN 1 0.0926 (2.35) 0.0500 0.020 (0.49) 0.0118 ...

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