cs5460 Cirrus Logic, Inc., cs5460 Datasheet
cs5460
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cs5460 Summary of contents
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... Energy, Instantaneous Power for single phase 2 or 3-wire power meter applica- RMS tions. The CS5460 interfaces to a low cost shunt or transformer to measure current, and resistive divider or transformer to measure voltage. The CS5460 features a bi-directional serial interface for communication with a micro-controller and a fixed-width programmable fre- quency output that is proportional to energy ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 ............................................................................... 15 .............................................................................. 15 ............................................................................. 15 ........................................................................ 15 ............................................................................ 16 ......................................................... 17 CS5460 DS279PP5 ...
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... Figure 4. Typical Connection Diagram (One-Phase 3-Wire)......................................................... 10 Figure 5. Data Flow....................................................................................................................... 11 Figure 6. Voltage Input Filter Roll-off ............................................................................................ 12 Figure 7. Current Input Filter Roll-off............................................................................................. 12 Figure 8. Multi-Phase System ....................................................................................................... 13 Figure 9. CS5460 Register Diagram ............................................................................................. 14 Figure 10. Command and Data Word Timing ............................................................................... 19 Figure 11. Oscillator Connection................................................................................................... 27 Figure 12. System Calibration of Offset. ....................................................................................... 28 Figure 13. System Calibration of Gain. ......................................................................................... 28 LIST OF TABLES Table 1 ...
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... Hz) (Gain = 10) IC (Gain = 50) (Note 5) EII (Gain = 10) (Gain = 50) (Gain = 10) (Gain = 50) (Note 1) VOS (Note 1) FSE {(VIN+) - (VIN-)} VIN (50, 60 Hz) IC (Note 5) EII (Note 1) VOS (Note 1) FSE CS5460 Min Typ Max Unit nV/° 100 %F.S. - DCLK 150 ...
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... PSRR (Gain = 50) PSRR -40 °C to +85 °C; VA+, VD ±10% VA-, DGND = 0 A Symbol V IH XIN SCLK V IL XIN SCLK out out out CS5460 Min Typ Max -2.4 - +2.5 - DCLK/1024 - - 0.5 - 2 ppm/° 100 - 2.4 2.5 2 ...
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... out (DGND = 0 V; See Note 8) Symbol (Notes 9 and 10) Positive Digital VD+ Positive Analog VA+ Negative Analog VA- (Note 11 and 12 OUT (Note 13) PDN All Analog Pins V INA All Digital Pins V IND stg CS5460 Min Typ Max Unit - - 0. 0 0 ± ...
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... SCLK Any Digital Output t fall SCLK Any Digital Output t ost SCLK Pulse Width High t 1 Pulse Width Low CS5460 Min Typ Max Unit 2.5 4.096 20 MHz 1.0 µ 100 µ 1.0 µs ...
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... CS SDI MSB t 3 SCLK SDO MSB SCLK 8 MSB - Figure 1. SDI Write Timing (Not to Scale) MSB - Figure 2. SDO Read Timing (Not to Scale) CS5460 LSB LSB DS279PP5 ...
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... RMS channel and to provide a 150mV voltage channel. With single supply, the CS5460 is designed to accommodate common mode signals of -0.25V to VA+. Figure 3 illustrates the CS5460 connected to a ser- signals. RMS vice to measure power in a single-phase 2-wire sys- tem while configuration. Figure 4 illustrates the CS5460 con- figured to measure power in a single-phase 3-wire system ...
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... To Service Figure 4. Typical Connection Diagram (One-Phase 3-Wire) 2.2 Performing Measurements The CS5460 performs measurements of instanta- neous current, instantaneous voltage, instantaneous power, energy, RMS current, and RMS voltage. These measurements are output as 24-bit signed and unsigned data formats as a percentage of full scale. The flow of data to perform these calcula- tions is shown in Figure 5 ...
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... Note that the filter’s response scales with MCLK frequency and K. The current channel contains a sinc sated by a short length FIR. When the converter is driven with a 4.096 MHz clock (K=1) the compos- ite filter response is given in Figure 7. CS5460 V* SINC RMS ...
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... sume that the maximum current is I and the maximum voltage is V utilize the full dynamic range of the CS5460, the sensor gains can be calculated as: 1600 1800 2000 where k and k v and current, respectively. The CS5460 is assumed the shunt resistor ...
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... The maxi- DS279PP5 mum frequency is therefore MCLK/K/8. A timing diagram for a multi-phase system is shown in Fig- ure 8. Phase - 00 = 370 or 0x172 Phase - 01 Phase - 10 Phase - 11 Pulse-Rate Register Period t = 0x401067 CS5460 for Integer N 8 MCLK/K Figure 8. Multi-Phase System 13 ...
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... SERIAL PORT OVERVIEW The CS5460’s serial port incorporates a state ma- chine with transmit/receive buffers. The state ma- chine interprets 8 bit command words on the rising edge of SCLK. Upon decoding of the command word the state machine performs the requested command or prepares for a data transfer of the ad- dressed register ...
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... the device is powered-down, this command will power-up the device. When powered-on, no computations will be running. If the part is already powered-on, all computations will be halted. DS279PP5 CS5460 15 ...
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... Designates calibration channel 00 = Not allowed 01 = Calibrate the current channel 10 = Calibrate the voltage channel 11 = Calibrate voltage and current channel simultaneously GC Designates gain calibration 0 = Normal operation 1 = Perform gain calibration OC Designates offset calibration 0 = Normal operation 1 = Perform offset calibration CS5460 DS279PP5 ...
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... Total energy value of last cycle RMS current value of last cycle RMS RMS voltage value of last cycle RMS Timebase Calibration Internal Use only † Status register Reserved Reserved Internal Use only † Internal Use Only † Interrupt mask register Internal Use Only † Reserved Reserved CS5460 17 ...
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... Serial Port Interface The CS5460’s serial interface consists of four con- trol lines: CS, SDI, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDI, Serial Data In, is the data signal used to trans- fer data to the converters ...
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... CS SCLK MSB SDI CS SCLK MSB SDI SDO DS279PP5 LSB MSB Command Time 8 SCLKs Write Cycle LSB Command Time 8 SCLKs MSB Read Cycle Figure 10. Command and Data Word Timing CS5460 LSB Data Time 24 SCLKs LSB Data Time 24 SCLKs 19 ...
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... SCLK (i.e., 8 bit valid command. Configuration Register: st fall- Offset Register: Gain Registers Pulse-Rate Register: Cycle-Counter Register: Timebase Register: Status Register: Mask Register Signed Registers Unsigned Registers Table 2. Internal Registers Default Value CS5460 0x000001 0x000000 0x400000 0x0FA000 0x000FA0 0x800000 0x000001 0x000000 0x000000 0x000000 DS279PP5 ...
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... DL0 and DL1 bits control the EOUT and EDIR pins. SI[1:0] Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt active low level (default) DS279PP5 PC1 PC0 PH0 SI1 SI0 IHPF iCPU K3 CS5460 EOD DL1 DL0 ...
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... Command is received. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0 -18 ..... -16 ..... Gain < 4.0. CS5460 -19 -20 -21 -22 - -17 -18 -19 -20 - DS279PP5 ...
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... CS5460 but can be in -18 -19 -20 -21 -22 2 ...
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... TBC 2. EDIR Res MATH EOR EOOR WDT VOD IOD -17 -18 -19 -20 - Res IOR 10 9 Res Res 2 1 LSD 0 CS5460 LSB -22 - VOR 8 Res 0 IC DS279PP5 ...
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... KHz EOUT pin rate. The bit can also be cleared by writing to the status register. This status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). DRDY Data Ready. Set at the end of a calibration or conversion cycle. DS279PP5 CS5460 25 ...
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... The time-out is preprogrammed to approximately 5 sec- onds. The countdown restarts each time the Energy register is read. Under typical situations, the Ener- CS5460 DS279PP5 ...
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... CMOS level signals. This amplifier works with sinusoidal inputs so there are no problems with slow edge times. DS279PP5 The CS5460 can be driven by a clock ranging from 2 MHz Table 2 shows the clock divide value K (default = 1) that the CS5460 needs to be pro- grammed with for normal operation Table 3 ...
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... Voltage Reference The CS5460 is specified for operation with a +2.5 V reference between the VREFIN and VA- pins. The converter includes an internal 2.5 V reference (60 ppm/°C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the de- vice. If higher accuracy/stability is required, an ex- ternal reference can be used. ...
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... VIN+ input pin. (If it was in- stalled, it would be called RP sides of the CS5460 input channels are not ground- ed (i.e., if VIN- and IIN- are connected in a differ- ential configuration) then it is appropriate to put protection resistors on these inputs as well. ...
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... KOhm. V 5.7 PCB Layout to provide for I The CS5460 should be placed entirely over an ana- log ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately ad- jacent to the digital portion of the chip. Note: ...
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... SDO pin in a high impedance state. CS should be changed when SCLK is low. Interrupt - When INT goes low it signals that an enabled event has occurred. INT is cleared (logic 1) by writing the appropriate command to the CS5460. Energy Output - The energy output pin output a fixed-width pulse rate output with a rate (programmable) proportional to energy ...
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... VA+ - The positive analog supply is nominally +5 V ±10% relative to VA-. PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level is 2.5 V with respect to the VA- pin. Reset - When reset is taken low, all internal registers are set to their default states connection. Pins should be left floating. CS5460 DS279PP5 ...
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... SEATING SIDE VIEW NOM MAX MIN -- 0.084 0.006 0.010 0.05 0.069 0.074 1.62 -- 0.015 0.22 0.323 0.335 7.90 0.307 0.323 7.40 0.209 0.220 5.00 0.026 0.030 0.55 0.0354 0.041 0.63 4° 8° JEDEC #: MO-150 END VIEW L PLANE MILLIMETERS NOM MAX -- -- 2.13 0.13 0.25 1.75 1.88 -- 0.38 8.20 8.50 7.80 8.20 5.30 5.60 0.65 0.75 0.90 1.03 0° 4° 8° CS5460 NOTE 2 ...
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