tda8031hl-c107 NXP Semiconductors, tda8031hl-c107 Datasheet - Page 22

• Manufacturer Part Number: tda8031hl-c107
• Description: Usb Smart Card Reader Otp Or Rom
• Manufacturer: NXP Semiconductors

Philips Semiconductors
If any of the status bits FER, OVR, PE, EA, TO1 or TO3
are set, then INT0 is LOW. The bit having caused the
interrupt is reset 2
during a read operation of the USR. If TBE/RBF is set and
if the mask bit DISTBE/RBF within UCR2 is not set, then
INT0 is also LOW. TBE/RBF is reset 2 clock cycles after
data has been written into the UTR, or 2 clock cycles after
data has been read from the URR, or when changing from
transmission mode to reception mode if the FIFO had not
been left full when going to transmission mode. If the Last
Character to Transmit (LCT) is used for transmitting the
last character, then TBE will not be set at the end of the
transmission.
Table 17 Programmable divider register (address 02H; read and write); note 1
Note
1. All bits are cleared after reset.
8.1.5.2
Table 18 UART configuration register 2 (address 03H; read and write); note 1
Note
1. All bits are cleared after reset.
2003 Jul 04
USB smart card reader (OTP or ROM)
ENINT1
PD7
27
7
UART configuration register 2
DISTBE/
RBF
PD6
f
26
int
6
cycles after the rising edge of RD
PD5
25
5
PD4
24
4
22
8.1.5
When working with a card, the following registers may be
used for programming some specific parameters:
8.1.5.1
The Programmable Divider Register (PDR) is used for
counting the cards clock cycles which form the ETU. It is
an autoreload 8-bit counter decounting from the
programmed value down to 0.
SAN
PD3
23
3
CARDS REGISTERS
Programmable divider register
AUTOCONV
PD2
22
2
TDA8030; TDA8031
CKU
PD1
21
1
Product specification
PSC
PD0
20
0