uda1338h-n1 NXP Semiconductors, uda1338h-n1 Datasheet
uda1338h-n1
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uda1338h-n1 Summary of contents
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... Multichannel audio coder-decoder Rev. 03 — 16 February 2005 1. General description The UDA1338H is a single-chip consisting of 4 plus 1 analog-to-digital converters and 6 digital-to-analog converters with signal processing features employing bitstream conversion techniques. The multichannel configuration makes the device eminently suitable for use in digital audio equipment which incorporates surround feature. ...
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... ADC current DAC analog supply f DAC current digital supply current f ADC f VOICE Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder 2 S-bus, MSB-justified, LSB-justified and two stereo) with programmable gain amplifiers stereo all voltages referenced to ground L Min. 2.7 2.7 2 kHz ...
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... A-weighted signal-to-noise ratio code = 0; A-weighted channel separation Ordering information Package Name Description QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 10 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder = all voltages referenced to ground L Min. Typ [1] [2] 2.5 1 ...
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... INTERFACE 30 VOLUME, MUTE, DE-EMPHASIS INTERPOLATION FILTER UDA1338H NOISE SHAPER 32 DAC DAC DAC DDA(DA) SSA(DA) Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder SSA(AD) ADCP ADCN ref ADC 1R PGA ADC 2R PGA TEST CLOCK 2 I ...
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... DO ADC 2 data output 13 DO ADC 1 data output 14 DIS ADC bit clock input 15 DI ADC word select input Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder 33 VOUT2P 32 VOUT1N 31 VOUT1P 30 I2C_L3 29 V DDD 28 V SSD ...
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... Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Description voice data output voice bit clock input voice word select input or output system clock input: 256f ...
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... IIC 8. Functional description 8.1 System clock The UDA1338H operates in slave mode only; this means that in all applications the system must provide either the system clock (the bit clock for the voice ADC) or the word clock. The audio ADC part, the voice ADC part and the DAC part can operate at different sampling frequencies (DAC-WS and ADC-WS modes) as well as a common frequency (SYSCLK, WSDA and DSD modes) ...
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... Fig 3. Schematic of audio ADC front-end 8.3 Voice analog-to-digital converter (voice ADC) The voice analog-to-digital front-end of the UDA1338H consists of a single-channel single-ended ADC with a fixed gain (26 dB) Low Noise Amplifier (LNA). Together with the digital variable gain amplification stage, the voice ADC provides optimal processing and reproduction of the microphone signal ...
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... This noise shaping technique enables high signal-to-noise ratios to be achieved. 8.8 Digital mixer The UDA1338H has 6 digital mixers inside the interpolator; see signals can be mixed with the I selected by the bits MIX[1:0]. ...
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... Dynamic Element Matching (DEM) algorithm scrambler circuit and DC current compensation circuit are implemented with the SDAC. 8.10 Power-on reset The UDA1338H has an internal power-on reset circuit which initializes the device; see Figure 5. All the digital sound processing features and the system controlling features are ...
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... Product data sheet V DDA(AD RESET V ref CIRCUIT 3.3 V DDD (V) 0 3.3 V DDA(AD) ( ref (V) 1.65 1.25 0. rst 250 s Figure 7 and Figure 8. Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder mgu585 mgu586 © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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LEFT BCK DATA MSB S-BUS FORMAT WS LEFT BCK DATA MSB B2 LSB MSB-JUSTIFIED FORMAT WS LEFT BCK DATA WS LEFT 20 19 BCK DATA MSB B2 WS ...
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BCK DATA MSB LSB MSB CH1 CH3 BCK DATA MSB LSB MSB CH1 CH3 BCK DATA MSB LSB MSB CH1 (1) Format 1. (2) ...
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... DATA MSB B2 Fig 9. Voice digital interface formats 8.13 DSD mode The UDA1338H can receive 2.8224 MHz DSD signals and generate 88.2 kHz multibit PCM signals as well as analog signal outputs. The configuration of the UDA1338H in the DSD mode is shown in DATADA2 left channel 2.8224 MHz ...
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... The UDA1338H has an L3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. The exchange of data and control information between the microcontroller and the UDA1338H is LSB first and is accomplished through a serial hardware L3-bus interface comprising the following pins: • ...
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... The device address consists of one byte with: • Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer; see • Address bit 2 to bit 7 representing a 6-bit device address. The address of the UDA1338H is 01 0100 (bit 2 to bit 7). Table 13: DOM Bit ...
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L3CLOCK L3MODE device address 0 1 L3DATA DOM bits Fig 11. Data write mode L3CLOCK L3MODE device address register address L3DATA DOM bits read prepare read Fig 12. Data read mode register address data byte 1 0 ...
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... Product data sheet Table 14): L3-bus write data Action First in time Bit 0 device address 0 0 D15 D7 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Figure 11. For writing data to a Figure 12. Table Latest in time Bit 1 Bit 2 Bit 3 Bit 4 Bit ...
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... The UDA1338H has an I with the I accessible via pin MCMODE with signal QMUTE. The exchange of data and control information between the microcontroller and the UDA1338H is accomplished through a serial hardware interface comprising the following pins as shown in • MCCLK: clock line with signal SCL • ...
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... C-bus 14. A LOW-to-HIGH transition of the data line while the clock is HIGH is Figure 15. At the acknowledge bit the data line is released by the Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Table 16 change of data allowed mbc621 © ...
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... Before any data is transmitted on the I addressed first. The addressing is always done with byte 1 transmitted after the start procedure. The UDA1338H acts as a slave receiver or a slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The UDA1338H device address is shown in ...
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... The format of the read cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address ‘0011 000’ and a logic 0 (write) for the R/W bit. 3. This is followed by an acknowledge (A) from the UDA1338H. 9397 750 14389 Product data sheet 2 ...
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... Then the microcontroller generates the device address ‘0011 000’ again, but this time followed by a logic 1 (read) of the R/W bit. An acknowledge is followed from the UDA1338H. 8. The UDA1338H sends 2 bytes data with the Most Significant (MS) byte first and then the Least Significant (LS) byte. After each byte an acknowledge is followed from the microcontroller (master). ...
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... Supplemental settings 30h 31h 9397 750 14389 Product data sheet Overview of register mapping …continued Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Function DAC channel 1 DAC channel 2 DAC channel 3 DAC channel 4 DAC channel 5 DAC channel 6 DAC mixing channel 1 DAC mixing channel 2 ...
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... Register mapping [1] Table 21: UDA1338H register mapping Add Function D15 D14 D13 D12 System settings [2] 00h system RST VFS1 VFS0 VCE - 01h audio ADC DC PAB PAA MTB and DAC subsystem 02h voice ADC - - - - system Status (read out only) ...
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... Table 21: UDA1338H register mapping …continued Add Function D15 D14 D13 D12 19h DAC mixing - - - - channel 1Ah DAC mixing ICS1 ICS0 - - channel 1Bh DAC mixing - - - - channel 1Ch DAC mixing ICS1 ICS0 - - channel 1Dh DAC mixing ...
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... DCE = 0, then the clock is disabled. DAP DAC power control. A 1-bit value to reduce the power consumption of the DAC. If bit DAP = 1, then the state is power-on; if bit DAP = 0 (default), then the state is power-off. Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder VCE ...
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... DC PAB PAA DAG FIL DVD Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Function 6.25 kHz to 12.5 kHz (default) 12.5 kHz to 25 kHz 25 kHz to 50 kHz reserved DAC Bit DVD = 0 Bit DVD = 1 256f 128f s s 384f 192f s s 512f ...
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... Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Table rate is used for 192 kHz s Table 31. Table Function 2 I S-bus format (default) LSB-justified format, 16 bits LSB-justified format, 20 bits LSB-justified format, 24 bits MSB-justified format ...
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... Voice ADC interface format. A 1-bit value to select the data interface format of the voice ADC. If bit VIF = 1, then mono-channel format; if bit VIF = 0 (default), then I BCK frequency of voice ADC bits BCK0 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder ...
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... DAC channel 1 and channel 2. If bit DS0 = 1, then power-down is ready and the clock may be disabled; if bit DS0 = 0, then power-down is not ready and the clock should not be disabled. Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Function high-pass filter off ...
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... MC4 MC3 MC2 MC1 CS4 CS3 CS2 CS1 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder MC4 MC3 MC2 MC1 CS4 CS3 CS2 CS1 Table 41. Table 42. ...
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... Interpolator volume control. An 8-bit value to program the volume attenuation of each channel. The range is from steps of 0.25 dB, from steps and Default 0000 0000; see Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Function all features (default) volume ...
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... Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder DE0 Function 0 no de-emphasis (default) 1 de-emphasis of 32 kHz 0 de-emphasis of 44.1 kHz 1 de-emphasis of 48 kHz 0 de-emphasis of 96 kHz 1 not used 0 not used 1 not used VC2 VC1 ...
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... DAC mixing channel 1, 3 and 5 registers (addresses 18h, 1Ah and 1Ch ICS1 ICS0 - VC7 VC6 VC5 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder DE1 DE0 VC4 VC3 VC2 ...
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... Default 0000; see Audio ADC input amplifier gain bits IA2 IA1 IB2 IB1 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder VC4 VC3 VC2 VC1 ...
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... Supplemental settings 1 register (address 30h PDT - - Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder IV4 IV3 IV2 IV1 IV1 IV0 ...
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... LNA. It should be noted that disabling the LNA requires a recovery time defined by the external RC circuit. If bit PDNLA = 1, then power-down; if bit PDNLA = 0 (default), then power-on. DAC dither control bits DITH1 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder seconds; if bit PDT = 0 s seconds ...
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... Product data sheet Limiting values supply voltage maximum crystal temperature storage temperature operating ambient temperature electrostatic discharge voltage Thermal characteristics Parameter thermal resistance from junction to ambient Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Conditions Min. [ [2] 2000 +2000 V [3] ...
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... ADC DAC kHz VOICE kHz; ADC DAC kHz VOICE audio and voice ADCs power-down DAC power-down with respect to V SSA(AD) Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder SS Min. Typ. Max. 2.7 3.3 3.6 2.7 3.3 3.6 2.7 3.3 3 ...
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... Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder SS Min. Typ. Max kHz; all voltages s Min ...
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... A-weighted code = 0; A-weighted at 0 dBFS digital input at 0 dBFS at 20 dBFS at 60 dBFS; A-weighted code = 0; A-weighted Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder = 48 kHz; all voltages s Min. Typ. Max. Unit - ...
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... MHz sys f 19.2 MHz sys f < 19.2 MHz sys f 19.2 MHz sys Figure 17 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder = 48 kHz; all voltages s Min. Typ. Max <0 110 - - 114 - Min. Typ. ...
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... L3DATA delay time for read data d(L3)R t L3DATA disable time for read data dis(L3)R 9397 750 14389 Product data sheet = +85 C; typical timing specified at sampling frequency amb Conditions WSV-out mode and 19 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Min. Typ. Max ...
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... To be suppressed by the input filter. t CWH Fig 16. System clock timing 9397 750 14389 Product data sheet = +85 C; typical timing specified at sampling frequency amb Conditions t CWL T sys Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Min. Typ. Max 400 ...
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... Product data sheet t t h(WS su(WS) t BCKL t d(DATAO-WS) t h(L3)A t CLK(L3 CLK(L3)H su(L3)A t su(L3)DA BIT 0 Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder t d(DATAO-BCK) t h(DATAO) t su(DATAI) t su(L3)A t h(L3)A T cy(CLK)(L3) t h(L3)DA BIT 7 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. t h(DATAI) mgs756 mgl723 ...
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... Product data sheet t CLK(L3)L t CLK(L3)H t su(L3)DA t h(L3)DA BIT 0 t h(L3 SU;DAT t SU;STA t HIGH Sr Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder t stp(L3 h(L3)D cy(CLK)L3 BIT dis(L3)R su(L3)R mgu015 HD;STA SU;STO P © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... 2.5 scale (1) ( 0.4 0.25 10.1 10.1 12.9 0.8 0.2 0.14 9.9 9.9 12.3 REFERENCES JEDEC JEITA Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ...
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... If wave soldering is used the following conditions must be observed for optimal results: 9397 750 14389 Product data sheet 2 called small/thin packages. Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder 3 350 mm so called © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , LBGA, LFBGA, SQFP, [3] , TFBGA, VFBGA, XSON , SO, SOJ [8] [9] [8] , PMFP , WQCCN..L Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable [5] [6] ...
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... Hot bar soldering or manual soldering is suitable for PMFP packages. 9397 750 14389 Product data sheet 10 C measured in the atmosphere of the reflow oven. The package Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Product data sheet - Table 1 Table 65 Table 66 Preliminary - specification Preliminary - specification Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder Doc. number Supersedes 9397 750 14389 UDA1338H_2 9397 750 10089 UDA1338H_1 9397 750 09319 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... Rev. 03 — 16 February 2005 UDA1338H Multichannel audio coder-decoder © Koninklijke Philips Electronics N.V. 2005. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Published in The Netherlands UDA1338H Multichannel audio coder-decoder Read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register mapping . . . . . . . . . . . . . . . . . . . . . . 23 Address mapping . . . . . . . . . . . . . . . . . . . . . . 23 Register mapping ...