uda1325 NXP Semiconductors, uda1325 Datasheet
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uda1325 Summary of contents
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... DATA SHEET UDA1325 Universal Serial Bus (USB) CODEC Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 1999 May 10 ...
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... Document references “USB Specification” “USB Device Class Definition for Audio Devices” “Device Class Definition for Human Interface Devices (HID)” “USB HID Usage Table” . “USB Common Class Specification” Preliminary specification UDA1325 ...
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... S output of the digital I/O possible for sampling the analog input signal at different sampling rates. The wide dynamic range of the bitstream conversion technique used in the UDA1325 for both the playback and recording channel guarantees a high audio sound quality. PACKAGE DESCRIPTION plastic shrink dual in-line package; 42 leads (600 mil) plastic quad fl ...
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... A-weighted at code 0000H 3 44.1 kHz; s PGA gain = kHz 1.0 V (RMS kHz ( Preliminary specification UDA1325 TYP. MAX. UNIT 5.0 5.25 V 3.3 3 tbf mA 360 0.0032 0. 3 dBA 0.66 ...
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... DIGITAL I/O MICRO- CONTROLLER FIFO AUDIO FEATURE PROCESSING DSP UPSAMPLE FILTERS TEST CONTROL BLOCK VARIABLE HOLD REGISTER 3rd-ORDER NOISE SHAPER LEFT DAC RIGHT DAC UDA1325 V DDI (10 SSI (11 SSE (12 DDE (13 DDO (23 SSO (24 DDA1 (29 SSA1 (30) 39 ...
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... LOW) supply voltage for operational amplifier operational amplifier ground O voltage output left channel I test control input (active HIGH) I asynchronous reset input of the test control block (active HIGH) O voltage output right channel 6 Preliminary specification UDA1325 DESCRIPTION ...
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... PLL ground I/O Port 0.0 of the microcontroller I data Input (digital) I/O Port 0.1 of the microcontroller I word select Input (digital) I/O Port 0.2 of the microcontroller I bit clock Input (digital) I/O Port 0.3 of the microcontroller I/O general purpose pin 2 or data output I/O Port 0.4 of the microcontroller 7 Preliminary specification UDA1325 DESCRIPTION ...
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... V SSI 10 V SSE 11 V DDE 12 GP1/DI 13 P2.0 14 GP5/WSI 15 P2.1 16 GP0/BCKI 17 P2.2 18 SCL 19 1999 May 10 UDA1325H Fig.2 Pin configuration (QFP64 package). 8 Preliminary specification UDA1325 51 VRP 50 ALE 49 VRN VINR 46 n. SSA2 43 VINL 42 V DDA2 41 V ref(AD ref(DA SSA1 ...
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... The functions of the PSIE include: synchronization pattern recognition, parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generation, PID verification/generation, address recognition and handshake evaluation/generation. The amount of bytes/packet on all endpoints is limited by the PSIE hardware to 8 bytes/packet, except for both isochronous endpoints (336 bytes/packet). 9 Preliminary specification UDA1325 intrinsic DD ...
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... The microcontroller does not handle the audio stream. The major task of the software process that is mapped upon the microcontroller control the different modules of the UDA1325 in such a way that it behaves as a USB device. The embedded 80C51 microcontroller is compatible with the 80C51 family of microcontrollers described in the 80C51 family single-chip 8-bit microcontrollers of “ ...
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... Q f /(2Q) osc 11 Preliminary specification UDA1325 SAMPLE FREQUENCY (kHz (not supported) 44.1 22.05 11.025 5.5125 SAMPLE FREQUENCY (kHz) (3) f /(256Q) osc ...
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... DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. ) the DSP knows four s 12 Preliminary specification DSP DOMAIN SAMPLE FREQUENCY (kHz UDA1325 ...
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... The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. Data transfer for the UDA1325 can only be in one direction, from microcontroller to ADAC to program its sound processing features and other functional features. ...
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... Table 7). 1999 May 10 0 audio feature registers (volume left, volume right, bass and treble) 1 not used 0 control registers 1 not used t halt address data byte #1 data byte #2 14 Preliminary specification UDA1325 DATA TRANSFER TYPE address MGD018 ...
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... DATA OF THE CONTROL REGISTER bit 0 15 Preliminary specification BIT0 REGISTER VR0 volume right VL0 volume left BB0 bass TR0 treble bit 7 REGISTER ADDRESS bit 7 MGS270 bit 7 REGISTER ADDRESS bit 7 MGS269 UDA1325 ...
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... LSB justifi adaptive 01 = fix state fix state fix state adaptive 1 = fixed 00 = lock after 512 samples 01 = lock after 2048 samples 10 = lock after 4096 samples 11 = lock after 16348 samples 1 s UDA1325 COMMENT select 0 select 00 select 1 select 00 = 44.1 kHz. When ...
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... Philips Semiconductors Universal Serial Bus (USB) CODEC Volume control The volume of the UDA1325 can be controlled from 0 dB down (in steps of 1 dB). Below 60 dB the audio signal is muted ( dB). The setting always referenced to the maximum available volume setting. Independant volume control of the left and right channel is possible (balance control). ...
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... Preliminary specification UDA1325 TREBLE (dB) FLAT SET MIN. SET MAX. SET ...
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... Preliminary specification UDA1325 BASS (dB) FLAT SET MIN. SET MAX. SET 1.1 0 1.1 0 2.4 0 2.4 0 3.7 0 3.7 0 5.2 0 5.2 0 6.8 0 6.8 0 8.4 0 8.4 0 10 ...
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... Universal Serial Bus (USB) CODEC Filter characteristics playback channel The overall filter characteristic of the UDA1325 in flat mode is given in Fig.4 (de-emphasis off). The overall filter characteristic of the UDA1325 includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC (f = 44.1 kHz) ...
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... The UDA1325 supports the standard I word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O option the UDA1325 device acts as a master, controlling the BCKO and WSO signals. Using the 6-pin digital I/O option GP2, GP3 and GP4 are output pins (master) and GP0, GP1 and GP5 are input pins (slave) ...
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Acrobat reader. white to force landscape pages to be ... WS LEFT BCK DATA MSB B2 WS LEFT BCK DATA WS ...
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... BIT PORT 3 LOW HIGH no error error no suspend suspend 23 Preliminary specification UDA1325 COMMENT general purpose pins 2 I C-bus COMMENT suspend input from USB interface during normal operation or input from restart circuit general purpose pin interrupt input from USB interface ...
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... DAh S1DAT 00 DBh S1ADR 8B Interrupts The UDA1325 supports up to five (of maximal 7) interrupt sources. Each interrupt source corresponds to an interrupt vector in the CPU program memory address space: Source 0: vector 0003h external interrupt 0 (INT0_N) RESET Source 1: vector 000Bh Timer 0 interrupt VALUE Source 2: vector 0013h external interrupt 1 (INT1_N) ...
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... ADIF (DC-filter S-bus input serial input format recording channel 25 Preliminary specification UDA1325 BIT VALUE (do not change it and 3 000 = 3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB ...
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... APLL reserved reset ADAC reset MMU reset digital I/O-interface reset ADIF reserved 26 Preliminary specification UDA1325 BIT VALUE ADC clock from APLL 1 = ADC clock from OSCAD 6 and ADC clock divided-by ADC clock divided-by ADC clock divided-by-4 ...
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... P3.3 (INT1_N) of the microcontroller power APLL power FSDAC power ADC left power ADC right power PGA left power PGA right 27 Preliminary specification UDA1325 BIT VALUE UPC control disabled (48 MHz oscillator is enabled UPC control enabled 2 6 and 4-pins I S ...
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... The total current drawn from the USB supply (for i.e. bus-powered operation of the UDA1325 application) must be less than 500 A in suspend mode. In order to reach that low current target, the total power dissipation of the UDA1325 can be reduced by disabling all internal clocks and switching off all internal analog modules. ...
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... USB processor. At this moment, several actions should be taken by the microcontroller: All analog modules of the UDA1325 must be switched off; this can be done by setting bits the power control register to ‘1’ and bit 0 of the clock shop register to ‘1’ ...
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... F0h F0h F1h F2h FAh F5h 30 Preliminary specification UDA1325 DATA PHASE write 1 byte read 1 byte write 1 byte read 1 byte write 1 byte read 1 byte read 1 byte (optional) read 1 byte (optional) read 1 byte (optional) read 1 byte ...
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... The format of the data phase is the same as for the set Power On Value endpoint enable command. Address Enable S ET MODE Command: F3h. Data: write 1 byte. 31 Preliminary specification UDA1325 BIT DESCRIPTION the value written becomes the device address a ‘1’ enables this function / ENABLE ...
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... X 0 Reserved Power On Value Data Receive/Transmit Error Code Setup Packet Data 0/1 Packet Previous Status not Read UDA1325 Control OUT Control IN Endpoint 1 OUT Endpoint 1 IN Endpoint 2 IN Endpoint 3 IN Endpoint 4 OUT Endpoint 5 IN Full/Empty ...
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... After each read, the internal buffer pointer is DESCRIPTION incremented by 1. The buffer pointer is not reset to the buffer start by the read buffer command. This means that reading a buffer can be interrupted by any other command (except for select endpoint). 33 Preliminary specification UDA1325 ...
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... All subsequent packets will be refused by returning a NACK to the host. When the microcontroller has read the data, it should free the buffer by the clear buffer command. When the buffer is cleared, new packets will be accepted. 34 Preliminary specification UDA1325 ...
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... AND THE CLOCK RATE BITS BIT FREQUENCY CR1 CR0 UDA1325 2 C-bus. CR0 CR1 AA SI STO STA ENS1 CR2 (kHz) 1200 600 400 300 150 100 75 3.9 ... 501 ...
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Acrobat reader. white to force landscape pages to be ... SDA t BUF t LOW t r SCL t HD;STA t HD;DAT P S ...
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... PARAMETER PARAMETER 37 Preliminary specification MIN. TYP. MAX. 0.5 V DDE 4 0 125 55 +150 3000 +3000 300 +300 CONDITIONS VALUE in free air 48 in free air 48 MIN. TYP. MAX. 4.75 5.0 5.25 3.0 3.3 3.6 0 0.5V DD 0.0 V DDE UDA1325 UNIT UNIT K/W K/W UNIT ...
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... connected to GND connected to V pin to GND 38 Preliminary specification MIN. TYP. MAX. 4.75 5.0 5.25 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 3.7 39.0 3.6 8.0 (2) 0.9 9.0 3.0 1.2 13.0 200 1.2 0.5 V DDI 2.8 3.6 0 0.2 0.8 2.5 0.8 2.0 20 0.3V 0.7V V DDE DDE 1 5 UDA1325 UNIT ( DDE ...
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... At start-up of the OSCAD oscillator start-up of the OSC48 oscillator. 4. Exclusive the IDDE current which depends on the components connected to the I/O pins. 1999 May 10 CONDITIONS MIN. TYP. 0.5V V DDA2 0.0 0.5V 12.5 0.5V 0.5V 11 2.0 39 Preliminary specification UDA1325 MAX. UNIT V DDA2 DDA2 k V DDA1 V DDA1 ...
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... May MHz 44.1 kHz; unless otherwise specified. osc s CONDITIONS steady-state drive 40 Preliminary specification UDA1325 MIN. TYP. MAX 110 1.3 2 11.97 12.00 12.03 0.9995 1.0000 1.0005 3.5 ...
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... R output resistance o C parasitic input capacitance XTAL1b i(XTAL1b) C parasitic input capacitance XTAL2b i(XTAL2b) I start-up current start 1999 May 10 CONDITIONS 2 C devices 41 Preliminary specification UDA1325 MIN. TYP. MAX. 0 100 4.7 4.0 4.7 4.0 4.7 4.0 5.0 250 1000 300 400 48 50 12.8 22.1 30.2 0.6 1.1 2 ...
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... PGA gain = 0 dB; note dB) i 1.0 V (RMS dB 0 PGA gain = PGA gain = 0 dB (RMS Preliminary specification UDA1325 MIN. TYP. MAX. 8.1920 11.2896 12.2880 50 10 (2) 25C ref (3) 1414 1000 708 355 178 ...
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... 44.1 kHz note input signal of 1 kHz (0 dB) 0.0032 at input signal of 1 kHz ( 60 dB) 3.2 A-weighting code 0000H . ref(DA) 43 Preliminary specification UDA1325 TYP. MAX. UNIT bits 0. ...
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... Philips Semiconductors Universal Serial Bus (USB) CODEC APPLICATION INFORMATION handbook, full pagewidth A(ext) V D(ext) Fig.8 Application diagram UDA1325H (continued in Fig.9). 1999 May 10 BCKI digital input WSI playback DI BCK digital input WS recording R48 L1 V USB 1 ...
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... C28 100 nF 100 nF L13 (63 V) (63 V) BLM32A07 C39 C18 47 F 100 nF R43 R26 ( Fig.9 Application diagram UDA1325H (continued from Fig.8). 1999 May ...
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... C39 C18 C24 C27 100 nF 100 100 nF R17 R25 R43 R26 (16 V) (63 V) ( Fig.10 Application diagram UDA1325PS PTC SCL 3 PCF85116 SDA R38 R39 ...
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... SOT270-1 1999 May scale (1) ( 1.3 0.53 0.32 38.9 14.0 0.8 0.40 0.23 38.4 13.7 REFERENCES JEDEC EIAJ 47 Preliminary specification 3.2 15.80 17.15 1.778 15.24 2.9 15.24 15.90 EUROPEAN PROJECTION UDA1325 SOT270 ( max. 0.18 1.73 ISSUE DATE 90-02-13 95-02-04 ...
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... 0.50 0.25 20.1 14.1 24.2 1 0.35 0.14 19.9 13.9 23.6 REFERENCES JEDEC EIAJ 48 Preliminary specification 18.2 1.0 1.95 0.2 0.2 0.1 17.6 0.6 EUROPEAN PROJECTION UDA1325 SOT319 detail X (1) ( 1.2 1 0.8 0.8 0 ISSUE DATE 95-02-04 97-08-01 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 49 Preliminary specification UDA1325 ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 1999 May 10 PACKAGE suitable not suitable not suitable suitable not recommended not recommended 50 Preliminary specification UDA1325 SOLDERING METHOD (1) WAVE REFLOW (2) suitable (3) suitable suitable (4)(5) suitable ...
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... I Philips. This specification can be ordered using the code 9398 393 40011. 1999 May components conveys a license under the Philips’ system provided the system conforms to the I 51 Preliminary specification UDA1325 2 C patent to use the 2 C specification defined by ...
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Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + ...