uda1344ts-n2 NXP Semiconductors, uda1344ts-n2 Datasheet

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uda1344ts-n2

Manufacturer Part Number
uda1344ts-n2
Description
Low-voltage Low-power Stereo Audio Codec With Dsp Features
Manufacturer
NXP Semiconductors
Datasheet
Product specification
Supersedes data of 2001 Mar 27
File under Integrated Circuits, IC01
DATA SHEET
UDA1344TS
Low-voltage low-power stereo
audio CODEC with DSP features
INTEGRATED CIRCUITS
2001 Jun 29

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uda1344ts-n2 Summary of contents

Page 1

... DATA SHEET UDA1344TS Low-voltage low-power stereo audio CODEC with DSP features Product specification Supersedes data of 2001 Mar 27 File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2001 Jun 29 ...

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... MSB-justified data output and LSB-justified 16, 18 and 20 bits data input. The UDA1344TS can be controlled either via static pins or via the L3 interface. In the L3 mode the UDA1344TS has special Digital Sound Processing (DSP) features in playback mode such as de-emphasis, volume control, bass boost, treble and soft mute. ...

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... The input voltage can (RMS) when the current through the ADC input pin is limited to approximately using a series resistor. 2. The input voltage to the ADC is inversely proportional to the supply voltage. 3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M. 4. The output of the DAC scales proportionally with the supply voltage. 2001 Jun 29 CONDITIONS MIN ...

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... ADC ADC DECIMATION FILTER DC-CANCELLATION FILTER DIGITAL INTERFACE DSP FEATURES INTERPOLATION FILTER NOISE SHAPER DAC DAC DDO V SSO V DDA(DAC) Fig.1 Block diagram. 4 Product specification UDA1344TS V ADCN V ref( dB/6 dB VINR SWITCH 8 MC1 21 MC2 20 MP5 13 MP2 14 L3-BUS MP3 INTERFACE ...

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... Product specification UDA1344TS ref( SSO 2 VINL 3 VOUTL 26 V ref( DDO VINR VOUTR ADCN DDA(DAC) V ADCP SSA(DAC) UDA1344TS MC1 8 21 MC2 MP1 MP5 DDD 10 19 DATAI V SSD DATAO 11 18 SYSCLK MP2 13 16 BCK MP3 14 15 ...

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... For MSB- and LSB-justified formats it is important to have a WS signal with a duty factor of 50%. Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1344TS consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 128. ...

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... Table 5 Mode control pins 108 s 3 shifts s Important: in the L3 mode the UDA1344TS is completely pin and function compatible with the UDA1340M. 7 Product specification UDA1344TS LSB-justified 16, 18 and 20 bits data input LSB-justified 16 and 20 bits data input. PIN MC2 PIN MC1 LOW ...

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... Philips Semiconductors Low-voltage low-power stereo audio CODEC with DSP features dbook, full pagewidth 2001 Jun 29 8 Product specification UDA1344TS ...

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... Philips Semiconductors Low-voltage low-power stereo audio CODEC with DSP features Static pin mode The UDA1344TS is set to static pin mode by setting both pins MC1 and MC2 to HIGH level. The controllable features in this mode are: System clock frequency selection Data input/output format selection De-emphasis and mute control Power-down and ADC input level selection ...

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... Philips Semiconductors Low-voltage low-power stereo audio CODEC with DSP features L3 mode The UDA1344TS is set to the L3 mode by setting both pins MC1 and MC2 to LOW level. The static pins in this mode are used for: ADC output overload detection L3 interface signal input ADC input voltage selection. ...

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... Fig.5. The maximum input clock and data rate is 64f All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1344TS after the eighth bit of a byte has been received. A multibyte data transfer is illustrated in Fig.6. ...

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... L3DATA t stp(L3) handbook, full pagewidth L3MODE t su(L3)D L3CLOCK L3DATA WRITE 2001 Jun 29 t CLK(L3)L t CLK(L3)H t su(L3)A t su(L3)DA t h(L3)DA BIT 0 Fig.4 Timing in address mode. t CLK(L3)L T cy(CLK)L3 t CLK(L3)H t h(L3)DA t su(L3)DA BIT 0 Fig.5 Timing in data transfer mode. 12 Product specification UDA1344TS t su(L3)A t h(L3)A T cy(CLK)(L3) BIT 7 MGL723 t stp(L3) t h(L3)D BIT 7 MGL882 ...

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... DE0 PC1 PC0 13 Product specification UDA1344TS data byte #2 address MGL725 REGISTER SELECTED SC = system clock frequency (2 bits); see Table data input format (3 bits); see Table filter (1 bit); see Table 18 REGISTER SELECTED VC = volume control (6 bits); see Table bass boost (4 bits); see Table treble (2 bits) ...

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... M1 and M0. Table 20 Bass boost settings BB3 BB2 BB1 BB0 SELECTION Product specification UDA1344TS dB in steps of 1 dB. VOLUME (dB ...

Page 15

... Table 24 Flat/min./max. switch MIN. (dB) MAX. (dB OWER CONTROL A 2-bit value to disable the ADC and/or DAC to reduce power consumption. Table 25 Power control settings 15 Product specification UDA1344TS M1 M0 SELECTION 0 0 fl min min max. SELECTION PC1 ...

Page 16

... all voltages referenced to ground; unless otherwise specified. L CONDITIONS operating ADC power-down operating DAC power-down DAC power-down operating DAC power-down ADC power-down 16 Product specification UDA1344TS MIN 3000 +3000 V 300 = 3 3.0 V; note 3 DDA CONDITIONS VALUE in free air 90 MIN ...

Page 17

... V SSA(DAC) ref(D) (THD + N)/S < 0 note 2 ) must be connected to the same external power supply unit. SS resistor must be connected in series with the DAC output in 17 Product specification UDA1344TS MIN. TYP. MAX. 0. 0.5 DDD DDD 0.5 0.2V DDD 10 10 0.85V DDD 0.4 0. ...

Page 18

... The input voltage can (RMS) when the current through the ADC input pin is limited to approximately using a series resistor. 2. The input voltage to the ADC is inversely proportional with the supply voltage. 3. The output voltage of the UDA1344TS differs from the output voltage of the UDA1340M. 4. The output of the DAC scales proportionally with the supply voltage. 2001 Jun ...

Page 19

... MHz sys f 19.2 MHz sys f < 19.2 MHz sys f 19.2 MHz sys T = cycle time of cy(s) sample frequency from BCK falling edge from WS edge for MSB-justified format 19 Product specification UDA1344TS MIN. TYP. MAX. UNIT 0.30T 0.70T ns sys sys 0.40T ...

Page 20

... CWH handbook, full pagewidth T sys handbook, full pagewidth WS t BCKH t r BCK T cy(BCK) DATAO DATAI 2001 Jun 29 t CWL Fig.7 System clock timing. t h(WS su(WS) t BCKL t d(DATAO-WS) Fig.8 Serial interface timing. 20 Product specification UDA1344TS MGL443 t d(DATAO-BCK) t h(DATAO) t su(DATAI) t h(DATAI) MGS756 ...

Page 21

... MP3 14 MP4 SSO V DDO C26 100 nF ( 100 F R25 ( DD1 Fig.9 Application diagram. 21 Product specification UDA1344TS V DD2 R28 1 C9 100 F (16 V) C29 100 nF ( ADCP V SSD V DDD ref(A) 4 C22 100 nF ( ...

Page 22

... 2.5 scale (1) ( 0.38 0.20 10.4 5.4 7.9 0.65 0.25 0.09 10.0 5.2 7.6 REFERENCES JEDEC EIAJ MO-150 detail 1.03 0.9 1.25 0.2 0.13 0.63 0.7 EUROPEAN PROJECTION Product specification UDA1344TS SOT341 ( 1.1 8 0.1 o 0.7 0 ISSUE DATE 95-02-04 99-12-27 ...

Page 23

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 23 Product specification UDA1344TS ...

Page 24

... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2001 Jun 29 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 24 Product specification UDA1344TS (1) REFLOW suitable suitable suitable suitable suitable ...

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... Product specification UDA1344TS DEFINITIONS These products are not Philips Semiconductors ...

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... Philips Semiconductors Low-voltage low-power stereo audio CODEC with DSP features 2001 Jun 29 NOTES 26 Product specification UDA1344TS ...

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... Philips Semiconductors Low-voltage low-power stereo audio CODEC with DSP features 2001 Jun 29 NOTES 27 Product specification UDA1344TS ...

Page 28

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...

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