pca9545ad NXP Semiconductors, pca9545ad Datasheet

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pca9545ad

Manufacturer Part Number
pca9545ad
Description
4-channel I2c Switch With Interrupt Logic And Reset
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
2. Features
The PCA9545A/45B/45C is a quad bidirectional translating switch controlled via the
I
individual SCx/SDx channel or combination of channels can be selected, determined by
the contents of the programmable control register. Four interrupt inputs, INT0 to INT3, one
for each of the downstream pairs, are provided. One interrupt output, INT, acts as an AND
of the four interrupt inputs.
An active LOW reset input allows the PCA9545A/45B/45C to recover from a situation
where one of the downstream I
LOW resets the I
does the internal power-on reset function.
The pass gates of the switches are constructed such that the V
the maximum high voltage which will be passed by the PCA9545A/45B/45C. This allows
the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9545A, PCA9545B and PCA9545C are identical except for the fixed portion of
the slave address.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any
PCA9545A/45B/45C
4-channel I
Rev. 06 — 19 March 2007
1-of-4 bidirectional translating switches
I
4 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I
Alternate address versions A, B and C allow up to a total of 12 devices on the bus for
larger systems or to resolve address conflicts
Channel selection via I
Power-up with all switch channels deselected
Low R
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
2
C-bus interface logic; compatible with SMBus standards
on
switches
2
C-bus state machine and causes all the channels to be deselected as
2
C-bus switch with interrupt logic and reset
2
C-bus, in any combination
2
C-buses is stuck in a LOW state. Pulling the RESET pin
2
C-bus
DD
pin can be used to limit
Product data sheet

Related parts for pca9545ad

pca9545ad Summary of contents

Page 1

PCA9545A/45B/45C 4-channel I Rev. 06 — 19 March 2007 1. General description The PCA9545A/45B/45C is a quad bidirectional translating switch controlled via the 2 I C-bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual ...

Page 2

... TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm Ordering options Topside mark Temperature range 9545A PCA9545AD PA9545A PA9545B PA9545C Rev. 06 — 19 March 2007 PCA9545A/45B/45C 2 C-bus switch with interrupt logic and reset 5 0.85 mm ...

Page 3

... NXP Semiconductors 4. Block diagram SC0 SC1 SC2 SC3 SD0 SD1 SD2 SD3 RESET SCL SDA INT0 to INT3 Fig 1. Block diagram of PCA9545A/45B/45C PCA9545A_45B_45C_6 Product data sheet 4-channel I PCA9545A/PCA9545B/PCA9545C SWITCH CONTROL LOGIC POWER-ON RESET INPUT FILTER Rev. 06 — 19 March 2007 PCA9545A/45B/45C ...

Page 4

... Fig 4. Pin configuration for HVQFN20 (transparent top view) PCA9545A_45B_45C_6 Product data sheet 4-channel SDA 3 18 SCL 4 17 INT0 INT 5 16 SD0 SC3 PCA9545AD SC0 6 15 SD3 INT1 7 14 INT3 8 13 SD1 SC2 SC1 9 12 SD2 INT2 SS 002aab165 terminal 1 ...

Page 5

... NXP Semiconductors 5.2 Pin description Table 3. Symbol A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 V SS INT2 SD2 SC2 INT3 SD3 SC3 INT SCL SDA V DD [1] HVQFN package die supply ground is connected to both the V pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and ...

Page 6

... NXP Semiconductors 6. Functional description Refer to 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9545A is shown in internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. ...

Page 7

... NXP Semiconductors 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9545A/45B/45C, which will be stored in the control register. If multiple bytes are received by the PCA9545A/45B/45C, it will save the last byte received. This register can be written and read via the I Fig 8. Control register 6.2.1 Control register defi ...

Page 8

... NXP Semiconductors 6.2.2 Interrupt handling The PCA9545A/45B/45C provides 4 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9545A/45B/45C and the interrupt output will be driven LOW. The channel does not need to be active for detection of the interrupt. A bit is also set in the control register ...

Page 9

... NXP Semiconductors 6.4 Power-on reset When power is applied to V PCA9545A/45B/45C in a reset condition until V reset condition is released and the PCA9545A/45B/45C registers and I machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, V 6.5 Voltage translation The pass gate transistors of the PCA9545A/45B/45C are constructed such that the V voltage can be used to limit the maximum voltage that will be passed from one I another ...

Page 10

... NXP Semiconductors 7. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...

Page 11

... NXP Semiconductors 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see SDA SCL MASTER ...

Page 12

... NXP Semiconductors 7.5 Bus transactions Data is transmitted to the PCA9545A/45B/45C control register using the Write mode as shown in SDA START condition Fig 14. Write control register Data is read from PCA9545A/45B/45C using the Read mode as shown in SDA START condition Fig 15. Read control register PCA9545A_45B_45C_6 Product data sheet ...

Page 13

... NXP Semiconductors 8. Application design-in information 2 I C-bus/SMBus master (1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a Fig 16. Typical application PCA9545A_45B_45C_6 Product data sheet 4-channel 2 5 SDA SDA SCL SCL INT RESET pull-up resistor is required. ...

Page 14

... NXP Semiconductors 9. Limiting values Table 6. In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V (ground = 0 V). SS Symbol tot T stg T amb [1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability ...

Page 15

... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics See Table 8 on page 16 for Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage ...

Page 16

... NXP Semiconductors Table 8. Static characteristics See Table 7 on page 15 for Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage ...

Page 17

... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics Symbol Parameter t propagation delay PD f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START HD;STA [2] condition t LOW period of the SCL clock LOW t HIGH period of the SCL clock ...

Page 18

... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 17. Definition of timing on the I SCL SDA RESET 50 % Fig 18. Definition of RESET timing START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 19. I C-bus timing diagram ...

Page 19

... NXP Semiconductors Fig 20. Expanded view of read input port register 12. Test information Fig 21. Test circuitry for switching times PCA9545A_45B_45C_6 Product data sheet 4-channel I SCL 2 1 SDA INPUT t v(INTnN INTN) INT V PULSE GENERATOR Definitions test circuit Load resistance Load capacitance including jig and probe capacitance. ...

Page 20

... NXP Semiconductors 13. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 21

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 22

... NXP Semiconductors HVQFN20: plastic thermal enhanced very thin quad flat package; no leads; 20 terminals; body 0.85 mm terminal 1 index area terminal 1 20 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 23

... NXP Semiconductors 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...

Page 24

... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...

Page 25

... NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 12. Acronym CDM DUT ESD HBM C-bus LSB MM MSB PCB POR SMBus ...

Page 26

... NXP Semiconductors 16. Revision history Table 13. Revision history Document ID Release date PCA9545A_45B_45C_6 20070319 • Modifications: Table 9 “Dynamic value for symbol t PCA9545A_45B_45C_5 20061017 PCA9545A_4 20060925 PCA9545A_3 20050303 (9397 750 14311) PCA9545A_2 20040929 (9397 750 13989) PCA9545A_1 20040728 (9397 750 13309) PCA9545A_45B_45C_6 Product data sheet ...

Page 27

... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

Page 28

... NXP Semiconductors 19. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2.1 Control register definition . . . . . . . . . . . . . . . . . 7 6.2.2 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . Characteristics of the I 7 ...

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