pca9535ecmttxg ON Semiconductor, pca9535ecmttxg Datasheet

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pca9535ecmttxg

Manufacturer Part Number
pca9535ecmttxg
Description
Pca9535e, Pca9535ec 16-bit Low-power I/o Expander For I2c Bus With Interrupt
Manufacturer
ON Semiconductor
Datasheet

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PCA9535ECMTTXG
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PCA9535E, PCA9535EC
16-bit Low-Power I/O
Expander for I
Interrupt
General Purpose parallel Input / Output (GPIO) expansion through the
I
Configuration (Input or Output selection); Input, Output and Polarity
Inversion (active−HIGH or active−LOW operation) registers. At
power on, all I/Os default to inputs. Each I/O may be configured as
either input or output by writing to its corresponding I/O configuration
bit. The data for each Input or Output is kept in its corresponding Input
or Output register. The Polarity Inversion register may be used to
invert the polarity if the read register. All registers can be read by the
system master.
I/O pull−up resistors removed, has greatly reduced power
consumption when the I/Os are held LOW.
high−impedance open−drain outputs at all the I/O pins.
output which is activated when any input state differs from its
corresponding input port register state. The interrupt output is used to
indicate to the system master that an input state has changed. The
power−on reset sets the registers to their default values and initializes
the device state machine.
I
the PCA9535E and PCA9535EC are the same as the PCA9655E. This
allows up to 64 of these devices in any combination to share the same
I
Features
© Semiconductor Components Industries, LLC, 2011
March, 2011 − Rev. 0
2
2
2
C−bus / SMBus.
C−bus slave address of the device. The I
C−bus/SMBus.
The PCA9535E and PCA9535EC devices provide 16 bits of
The PCA9535E and PCA9535EC consist of two 8−bit
The PCA9535E, identical to the PCA9655E but with the internal
The PCA9535EC is identical to the PCA9535E but with
The PCA9535E and PCA9535EC provide an open−drain interrupt
Three hardware pins (AD0, AD1, AD2) are used to configure the
Noise Filter on SCL/SDA Inputs
No Glitch on Power−up
Internal Power−on Reset
64 Programmable Slave Addresses using Three
Address Pins
16 I/O Pins which Default to 16 Inputs
V
SDA Sink Capability: 30 mA
5.5 V Tolerant I/Os
Polarity Inversion Register
Active LOW Interrupt Output
Low Standby Current
DD
Operating Range: 1.65 V to 5.5 V
2
C Bus with
2
C−bus slave addresses of
1
I
ESD Performance: 3000 V Human Body Model, 400 V
Machine Model
These are Pb−Free Devices
2
C SCL Clock Frequencies Supported:
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Standard Mode: 100 kHz
Fast Mode: 400 kHz
Fast Mode +: 1 MHz
CASE 485BG
DW SUFFIX
CASE 751E
CASE 948H
(Note: Microdot may be in either location)
MT SUFFIX
TSSOP−24
DT SUFFIX
SOIC−24
QFN24
XXXX
A
WL, L
YY, Y
WW, W = Work Week
G or G
1
ORDERING INFORMATION
http://onsemi.com
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
Publication Order Number:
PCA9535E(C)
DIAGRAMS
AWLYYWWG
AWLYYWWG
MARKING
9535E(C)
PCA95
35E(C)
ALYWG
PCA
PCA9535E/D
G

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pca9535ecmttxg Summary of contents

Page 1

PCA9535E, PCA9535EC 16-bit Low-Power I/O 2 Expander for I C Bus with Interrupt The PCA9535E and PCA9535EC devices provide 16 bits of General Purpose parallel Input / Output (GPIO) expansion through the 2 I C−bus / SMBus. The PCA9535E and ...

Page 2

PCA9535E PCA9535EC AD0 AD1 AD2 SCL INPUT FILTER SDA V DD POWER−ON RESET V SS data from shift register configuration register data from D Q shift register FF write configuration CK Q pulse write pulse read pulse data from shift ...

Page 3

INT 1 AD1 2 AD2 3 4 IO0_0 IO0_1 5 PCA9535E IO0_2 6 PCA9535EC 7 IO0_3 IO0_4 8 IO0_5 9 IO0_6 10 11 IO0_7 Figure 3. SOIC24 / TSSOP24 Table 1. PIN DESCRIPTIONS SOIC24, TSSOP24 Symbol INT ...

Page 4

Table 2. MAXIMUM RATINGS Symbol V DC Supply Voltage DD V Input / Output Pin Voltage I/O I Input Current I I Output Current Supply Current Ground Current GND P Total Power Dissipation TOT ...

Page 5

Table 4. DC ELECTRICAL CHARACTERISTICS Symbol Parameter SUPPLIES I Standby Current STB V Power−On Reset Voltage (Note 6) POR INPUT SCL; INPUT / OUTPUT SDA V High−Level Input Voltage IH V Low−Level Input Voltage IL I Low−Level Output Current OL ...

Page 6

Table 5. AC ELECTRICAL CHARACTERISTICS Symbol Parameter f SCL Clock Frequency SCL t Bus−Free Time between a STOP and START BUF Condition t Hold Time (Repeated) START Condition HD:STA t Setup Time for a Repeated START Condition SU:STA t Setup ...

Page 7

Device Address Before the bus master can access a slave device, it must send the address of the slave it is accessing and the operation it wants to perform (read or write) following a START condition. The slave address of ...

Page 8

Table 6. PCA9535E AND PCA9535EC ADDRESS MAP Address Input AD2 AD1 AD0 VDD VDD SDA SCL SCL GND SCL SCL VDD SCL SDA GND SCL SDA VDD SDA SCL GND SDA SCL VDD SDA SDA GND SDA SDA VDD SCL ...

Page 9

Command Byte During a write transmission, the address byte is followed by the command byte. The command byte determines which of the following registers will be written or read. Table 7. COMMAND BYTE COMMAND 0 Input Port 0 1 Input ...

Page 10

Registers 4 and 5: Polarity Inversion Registers These registers allow the polarity of the data in the input port registers to be inverted. The input port data polarity will Table 12. POLARITY INVERSION PORT 0 REGISTER Bit 7 6 Symbol ...

Page 11

Writing to the Port Registers To transmit data to the PCA9535E/PCA9535EC, the bus master must first send the device address with the least significant bit set to logic 0 (see Figure 5 “PCA9535E and PCA9535EC device address”). The command byte ...

Page 12

SDA START condition R/W acknowledge from slave slave address (cont (repeated) R/W START condition acknowledge from slave Remark: Transfer can ...

Page 13

Interrupt Output The open−drain interrupt output is activated when an I/O pin configured as an input changes state. The interrupt is deactivated when the input pin returns to its previous state or when the Input Port register is read (see ...

Page 14

V DD LED LEDn Figure 12. High Value Resistor in Parallel with the LED 2 Characteristics of the I C−bus 2 The I C−bus is meant for 2−way, 2−line communication between different ICs or modules. The two lines are the ...

Page 15

System Configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the SDA SCL MASTER SLAVE TRANSMITTER/ RECEIVER RECEIVER Acknowledge The number of data bytes transferred between the START and the ...

Page 16

START bit 7 protocol condition MSB (S) (A7 SU;STA LOW HIGH SCL t BUF t r SDA t HD;STA Rise and fall times refer to V and Figure 19. I SCL t v(Q) IOn ...

Page 17

... ORDERING INFORMATION Device PCA9535EDWR2G PCA9535EDTR2G PCA9535EMTTXG PCA9535ECDWR2G PCA9535ECDTR2G PCA9535ECMTTXG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Package SOIC−24 (Pb−Free) TSSOP−24 (Pb−Free) QFN24 (Pb−Free) SOIC−24 (Pb− ...

Page 18

D 24X 0.010 (0.25 −T− SEATING G PLANE 22X PACKAGE DIMENSIONS SOIC−24 CASE 751E−04 ISSUE E 13 −B− P 12X 0.010 (0.25 ...

Page 19

L PIN 1 IDENT. 1 0.15 (0.006 0.10 (0.004) −T− SEATING D PLANE K K1 Ç Ç Ç Ç Ç Ç É É É J1 Ç Ç Ç ...

Page 20

... 0.05 C NOTE 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...

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