pca9506 NXP Semiconductors, pca9506 Datasheet
pca9506
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pca9506 Summary of contents
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... The internal Power-On Reset (POR) or hardware reset (RESET) pin initializes the 40 I/Os as inputs. Three address select pins configure one of 8 slave addresses. The PCA9506 is available in 56-pin TSSOP and HVQFN packages and is specified over the +85 C industrial temperature range. ...
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... Name Description TSSOP56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm HVQFN56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT 2 C-bus state machine) Version SOT364-1 SOT684-1 8 0.85 mm © ...
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... Philips Semiconductors 5. Block diagram SCL SDA RESET All I/Os are set to inputs at power-up and RESET. Fig 1. Block diagram of PCA9506 9397 750 14939 Product data sheet 2 40-bit I C-bus I/O port with RESET, OE, and INT PCA9506 LOW PASS 2 I C-BUS INPUT CONTROL ...
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... output port register input port register polarity inversion register data from pulse Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT configuration port register data (Cx[y]) output port register data (Ox[y ESD protection diode V SS Mx[y] INTERRUPT INT ...
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... PCA9506DGG IO1_2 15 16 IO1_3 IO1_4 IO1_5 19 IO1_6 20 21 IO1_7 IO2_0 IO2_1 IO2_2 25 26 IO2_3 Rev. 01 — 14 February 2006 PCA9506 56 RESET 55 INT 54 IO4_7 53 IO4_6 52 IO4_5 IO4_4 49 IO4_3 48 IO4_2 47 IO4_1 IO4_0 44 IO3_7 43 IO3_6 42 ...
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... Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT 42 IO4_3 41 IO4_2 40 IO4_1 IO4_0 37 IO3_7 36 IO3_6 35 IO3_5 ...
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... The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.2 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9506, which will be stored in the Command register. Fig 6. Command register 9397 750 14939 Product data sheet ...
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... At power-up, this register defaults to 0x80, with the AI bit set to logic 1, and the lowest 7 bits set to logic 0. During a write operation, the PCA9506 will acknowledge a byte sent to OPx, PIx, and IOCx and MSKx registers, but will not acknowledge a byte sent to the IPx registers since these are read-only registers ...
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... Rev. 01 — 14 February 2006 PCA9506 Description Input Port register bank 0 Input Port register bank 1 Input Port register bank 2 Input Port register bank 3 Input Port register bank 4 reserved for future use reserved for future use reserved for future use Output Port register bank 0 ...
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... R XXXX XXXX* I3[7:0] R XXXX XXXX* I4[7:0] R XXXX XXXX* Rev. 01 — 14 February 2006 PCA9506 Description Mask Interrupt register bank 0 Mask Interrupt register bank 1 Mask Interrupt register bank 2 Mask Interrupt register bank 3 Mask Interrupt register bank 4 reserved for future use reserved for future use reserved for future use ...
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... R/W 0000 0000* P3[7:0] R/W 0000 0000* P4[7:0] R/W 0000 0000* Rev. 01 — 14 February 2006 PCA9506 Description Output Port register bank 0 Output Port register bank 1 Output Port register bank 2 Output Port register bank 3 Output Port register bank 4 Description Polarity Inversion register bank 0 Polarity Inversion register bank 1 ...
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... M2[7:0] R/W 1111 1111* M3[7:0] R/W 1111 1111* M4[7:0] R/W 1111 1111 internal Power-On Reset (POR) holds the PCA9506 in DD has reached that point, the reset condition is released DD POR 2 C-bus state machine will initialize to their default states. must be lowered below 0 reset the device. DD ...
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... The robust state machine does not respond until it sees a valid START condition and the 50 ns noise filter will filter out any insertion glitches. The PCA9506 will not cause corruption of active data on the bus, nor will the device be damaged or cause damage to devices already on the bus when similar featured devices are being used ...
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... C-bus I/O port with RESET, OE, and INT 2 C-bus Figure SDA SCL data line change stable; of data data valid allowed Figure 8). S START condition Figure 9). Rev. 01 — 14 February 2006 PCA9506 7). mba607 SDA SCL P STOP condition mba608 © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Fig 10. Acknowledgement on the I 8.4 Bus transactions Data is transmitted to the PCA9506 registers using Write Byte transfers (see Figure 12, and Receive Byte transfers (see 9397 750 14939 ...
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SDA output bank START condition register bank 0 R/W AI ...
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SDA START condition R acknowledge from slave ...
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... IO0_1 RESET IO0_2 INT IO0_3 OE IO0_4 IO0_5 IO1_0 IO3_7 A2 IO4_0 A1 A0 IO4_7 V SS ALPHA NUMERIC KEYPAD Rev. 01 — 14 February 2006 PCA9506 SUB-SYSTEM 1 (e.g., temp sensor) INT SUB-SYSTEM 2 (e.g., counter) RESET A controlled ENABLE switch (e.g., CBT device) B SUB-SYSTEM 3 (e.g., alarm system) ALARM LED MATRIX 002aab500 © ...
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... [1] no load 0 Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT Min Max 0 0.5 5 0.5 5 0.5 5 +50 - 500 - 1100 - 500 65 +150 40 +85 ...
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... Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT Min Typ Max 0 0 ...
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... Product data sheet 2 40-bit I Conditions Standard mode 2 I Min [1] 0 4.7 4.0 4.7 4.0 0 [2] 0.1 0.1 250 4.7 4.0 [4] [5] - [4] [5] - [7] - output - output - - 100 0 100 Rev. 01 — 14 February 2006 PCA9506 C-bus I/O port with RESET, OE, and INT 2 Fast mode I C-bus C-bus Max Min Max 100 0 400 - 3.45 0.1 0.9 3.45 0.1 0.9 - 100 - - 1 ...
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... MSB (A6) (R/W) (A7 LOW HIGH 1 /f SCL VD;DAT SU;DAT HD;DAT . IH Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT is specifi HD;STA SU;STA SU;STO Sr 002aaa986 STOP acknowledge condition (A) ( VD;ACK SU;STO 002aab175 © ...
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... PULSE DUT GENERATOR load resistance = load capacitance includes jig and probe capacitance = termination resistance should be equal to the output impedance Z Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT ACK or read cycle t rst w(rst) t rst ...
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... 2 scale (1) ( 0.2 0.2 14.1 6.2 8.3 0.5 1 0.1 0.1 13.9 6.0 7.9 REFERENCES JEDEC JEITA MO-153 Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT SOT364 detail 0.8 0.50 0.5 0.25 0.08 0.1 0.4 0.35 0.1 EUROPEAN ...
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... 4.45 8.1 4.45 0.5 0.5 6.5 6.5 4.15 7.9 4.15 0.3 REFERENCES JEDEC JEITA MO-220 - - - Rev. 01 — 14 February 2006 PCA9506 C-bus I/O port with RESET, OE, and INT SOT684 detail 0.05 0.1 0.1 0.05 EUROPEAN ISSUE DATE PROJECTION 01-08-08 02-10-22 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... If wave soldering is used the following conditions must be observed for optimal results: 9397 750 14939 Product data sheet 2 40-bit I C-bus I/O port with RESET, OE, and INT 2 called small/thin packages. Rev. 01 — 14 February 2006 PCA9506 3 350 mm so called © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... Product data sheet 40-bit I Suitability of surface mount IC packages for wave and reflow soldering methods [3] , LBGA, LFBGA, SQFP, [8] [9] [8] , PMFP , WQCCN..L Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT Soldering method Wave Reflow not suitable suitable [4] not suitable suitable ...
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... Power-On Reset Pulse Width Modulation Redundant Array of Independent Disks Data sheet status Change notice Product data sheet - Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT Doc. number Supersedes 9397 750 14939 - © Koninklijke Philips Electronics N.V. 2006. All rights reserved. ...
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... Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of Koninklijke Philips Electronics N.V. Rev. 01 — 14 February 2006 PCA9506 2 C-bus I/O port with RESET, OE, and INT © Koninklijke Philips Electronics N.V. 2006. All rights reserved ...
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... No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 February 2006 Document number: 9397 750 14939 Published in The Netherlands PCA9506 ...