pca9672

Manufacturer Part Numberpca9672
DescriptionPca9672 Remote 8-bit I/o Expander For Fm I?c-bus With Interrupt And Reset
ManufacturerNXP Semiconductors
pca9672 datasheet
 


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PCA9672
Remote 8-bit I/O expander for Fm+ I
reset
Rev. 02 — 6 July 2007
1. General description
The PCA9672 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I
family.
The PCA9672 is a drop-in upgrade for the PCF8574 providing higher Fast-mode Plus
(Fm+) I
dimming of LEDs, higher I
can be on the bus without the need for bus buffers, higher total package sink capacity
(200 mA versus 100 mA) that supports having all LEDs on at the same time and more
device addresses (16 versus 8) are available to allow many more devices on the bus
without address conflicts.
The difference between the PCA9672 and the PCF8574 is that the A2 address pin is
replaced by the RESET input on the PCA9672.
The device consists of an 8-bit quasi-bidirectional port and an I
PCA9672 has low current consumption and include latched outputs with 25 mA high
current drive capability for directly driving LEDs.
The PCA9672 possesses an interrupt line (INT) that can be connected to the interrupt
logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can
inform the microcontroller if there is incoming data on its ports without having to
communicate via the I
The internal Power-On Reset (POR), hardware reset pin (RESET), or Software Reset
sequence initializes the I/Os as inputs.
2. Features
I
1 MHz I
I
Compliant with the I
I
SDA with 30 mA sink capability for 4000 pF buses
I
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
I
8-bit remote I/O pins that default to inputs at power-up
I
Latched outputs with 25 mA sink capability for directly driving LEDs
I
Total package sink capability of 200 mA
I
Active LOW open-drain interrupt output
I
16 programmable slave addresses using 2 address pins
I
Readable device ID (manufacturer, device type, and revision)
2
C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
2
C-bus drive (30 mA versus 3 mA) so that many more devices
2
C-bus.
2
C-bus interface
2
C-bus Fast and Standard modes
2
C-bus with interrupt and
Product data sheet
2
C-bus) and is a part of the Fast-mode Plus
2
C-bus interface. The

pca9672 Summary of contents

  • Page 1

    ... The difference between the PCA9672 and the PCF8574 is that the A2 address pin is replaced by the RESET input on the PCA9672. The device consists of an 8-bit quasi-bidirectional port and an I PCA9672 has low current consumption and include latched outputs with 25 mA high current drive capability for directly driving LEDs ...

  • Page 2

    ... Package mark Name Description 672 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 PCA9672D SO16 plastic small outline package; 16 leads; body width 7.5 mm TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm Rev. 02 — 6 July 2007 PCA9672 2 ...

  • Page 3

    ... Block diagram INT AD0 AD1 SCL SDA RESET Fig 1. Block diagram of PCA9672 data from Shift Register data to Shift Register Fig 2. Simplified schematic diagram PCA9672_2 Product data sheet Remote 8-bit I/O expander for Fm+ I PCA9672 INTERRUPT LOGIC 2 INPUT ...

  • Page 4

    ... P0 PCA9672PW Fig 4. Pin configuration for TSSOP16 12 SCL 11 INT PCA9672BS 002aac325 Description address input 0 address input 1 reset input (active LOW) quasi-bidirectional I/O 0 quasi-bidirectional I/O 1 quasi-bidirectional I/O 2 quasi-bidirectional I/O 3 supply ground quasi-bidirectional I/O 4 quasi-bidirectional I/O 5 quasi-bidirectional I/O 6 © NXP B.V. 2007. All rights reserved. ...

  • Page 5

    ... PCA9672 is shown in addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and AD0. Address values depending on AD1 and AD0 can be found in address Remark: When using the PCA9672 reserved I caution since they can interfere with: • “reserved for future use” I 1111 111) • ...

  • Page 6

    ... V DD 7.2 Software Reset Call, and device ID addresses Two other different addresses can be sent to the PCA9672. • General Call address: allows to reset the PCA9672 through the I reception of the right I information. • Device ID address: allows to read ID information from the device (manufacturer, part identification, revision). See information ...

  • Page 7

    ... The PCA9672 acknowledges this value only. If the byte is not equal to 06h, the PCA9672 does not acknowledge it. If more than 1 byte of data is sent, the PCA9672 does not acknowledge any more. 5. Once the right byte has been sent and correctly acknowledged, the master sends a ...

  • Page 8

    ... NXP). • 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the category ID and the 6 LSBs with the feature ID (for example, for example PCA9672 8-bit quasi-output I/O expander). • 3 bits with the die revision, assigned by manufacturer (for example, Rev X). ...

  • Page 9

    ... The PCA9672 acknowledges and the master sends the data byte for and is acknowledged by the PCA9672. The 8-bit data is presented on the port lines after it has been acknowledged by the PCA9672. ...

  • Page 10

    ... I trt(pu) t d(rst) data from port A DATA 1 R/W acknowledge from slave DATA 2 DATA h(D) su(D) t d(rst) Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset data acknowledge acknowledge from slave from slave t t v(Q) DATA 1 VALID DATA 2 VALID ...

  • Page 11

    ... PCA9672 registers and I states. Thereafter V 8.5 Interrupt output (INT) The PCA9672 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see chips a kind of master function which can initiate an action elsewhere in the system. An interrupt is generated by any rising or falling edge of the port inputs. After time t signal INT is valid ...

  • Page 12

    ... Remote 8-bit I/O expander for Fm C-bus Figure SDA SCL data line stable; data valid Figure 16.) S START condition Figure 17). Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset 15). change of data allowed mba607 P STOP condition © NXP B.V. 2007. All rights reserved. SDA SCL mba608 ...

  • Page 13

    ... TRANSMITTER/ RECEIVER TRANSMITTER RECEIVER data output by transmitter data output by receiver SCL from master 1 S START condition 2 C-bus Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset MASTER MASTER TRANSMITTER/ MULTIPLEXER RECEIVER SLAVE not acknowledge acknowledge 2 8 clock pulse for acknowledgement 2 ...

  • Page 14

    ... INT RESET AD0 AD1 V DD SDA SCL CORE INT PROCESSOR RESET AD0 AD1 Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset Figure 19, P0 and P1 are inputs, and temperature sensor P1 battery status P2 control for latch P3 control for switch ...

  • Page 15

    ... Rev. 02 — 6 July 2007 2 C-bus with interrupt and reset Conditions Min operating 40 Min Typ 2 260 = 1 MHz kHz [1] - 1.8 0 PCA9672 Max Unit +6 V 100 mA 400 mA 5 400 mW 100 mW +150 C +85 C Max Unit 5.5 V 500 2.0 V +0. 5 © ...

  • Page 16

    ... see Figure Figure 13 0 C-bus logic with V < V and set all I/Os to logic 1 (with current source POR Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset Min Typ Max 200 30 250 300 0.5 1 ...

  • Page 17

    ... PCA9672 Unit 2 I C-bus Max 0 1000 kHz 0 0. 450 0 120 ns - 120 © NXP B.V. 2007. All rights reserved. ...

  • Page 18

    ... LOW HIGH 1 /f SCL SU;DAT HD;DAT and Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset of the SCL signal) in order to IL STOP bit 0 acknowledge condition (R/W) (A) ( VD;DAT VD;ACK SU;STO 002aab175 ACK or read cycle t ...

  • Page 19

    ... 3.1 1.75 3.1 1.75 0.5 1.5 2.9 1.45 2.9 1.45 REFERENCES JEDEC JEITA MO-220 - - - Rev. 02 — 6 July 2007 2 C-bus with interrupt and reset detail 0.5 0.05 0.1 1.5 0.1 0.05 0.3 EUROPEAN PROJECTION PCA9672 SOT758 ISSUE DATE 02-03-25 02-10-21 © NXP B.V. 2007. All rights reserved ...

  • Page 20

    ... C-bus with interrupt and reset detail 1.1 1.1 1.4 0.25 0.25 0.4 1.0 0.043 0.043 0.055 0.01 0.01 0.016 0.039 EUROPEAN PROJECTION PCA9672 SOT162 ( 0.9 0 0.035 0.004 0.016 ISSUE DATE 99-12-27 03-02-19 © NXP B.V. 2007. All rights reserved ...

  • Page 21

    ... Rev. 02 — 6 July 2007 2 C-bus with interrupt and reset detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION PCA9672 SOT403 ( 0.40 8 0.1 o 0.06 0 ISSUE DATE 99-12-27 03-02-18 © NXP B.V. 2007. All rights reserved ...

  • Page 22

    ... Inspection and repair • Lead-free soldering versus PbSn soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCA9672_2 Product data sheet Remote 8-bit I/O expander for Fm+ I Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset © NXP B.V. 2007. All rights reserved ...

  • Page 23

    ... Lead-free process (from J-STD-020C) Package reflow temperature ( C) 3 Volume (mm ) < 350 260 260 250 Figure 26. Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset Figure 26) than a PbSn process, thus 350 220 220 350 to 2000 > 2000 260 260 250 245 ...

  • Page 24

    ... Identification Least Significant Bit Machine Model Most Significant Bit Programmable Logic Controller Pulse Width Modulation Redundant Array of Independent Disks Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset peak temperature time 001aac844 © NXP B.V. 2007. All rights reserved. ...

  • Page 25

    ... Legal texts have been adapted to the new company name where appropriate. • Table 1 “Ordering – changed Topside mark for PCA9672BS from “9672” to “672” – changed Topside mark for PCA9672PW from “9672” to “PCA9672” • Table 5 “Static – sub-section “Supplies”: changed I – ...

  • Page 26

    ... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 6 July 2007 PCA9672 2 C-bus with interrupt and reset © NXP B.V. 2007. All rights reserved ...

  • Page 27

    ... Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.1 Address map 7.2 Software Reset Call, and device ID addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2.1 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.2 Device ID (PCA9672 ID field I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 9 8.1 Quasi-bidirectional I/O architecture . . . . . . . . . 9 8.2 Writing to the port (Output mode 8.3 Reading from a port (Input mode 8.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11 8.5 Interrupt output (INT 8.6 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ...