adv7123-ep Analog Devices, Inc., adv7123-ep Datasheet
adv7123-ep
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adv7123-ep Summary of contents
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... The ADV7123-EP has additional video control signals: composite SYNC and BLANK . The ADV7123-EP also has a power save mode. The ADV7123-EP is fabricated CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7123-EP is available in a 48-lead LFCSP package ...
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... ADV7123-EP TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Dynamic Specifications ............................................................... 4 REVISION HISTORY 7/10—Revision 0: Initial Version Timing Specifications ...................................................................5 Absolute Maximum Ratings ............................................................7 ESD Caution...................................................................................7 Pin Configuration and Function Descriptions ..............................8 Outline Dimensions ....................................................................... 10 ...
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... K × (0x3FFH) and K = 7.9896. REF SET Rev Page ADV7123- unless otherwise noted; T MIN MAX Unit Test Conditions/Comments Bits R = 680 Ω SET LSB R = 680 Ω SET LSB R = 680 Ω SET V V μ 0 ...
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... ADV7123-EP DYNAMIC SPECIFICATIONS 1.235 REF SET Table 2. Parameter 1 AC LINEARITY Spurious-Free Dynamic Range to Nyquist Single-Ended Output MHz 1.00 MHz CLK OUT MHz 2.51 MHz CLK OUT MHz 5.04 MHz CLK OUT MHz 20.2 MHz CLK OUT f = 100 MHz ...
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... These maximum/minimum specifications are guaranteed by characterization over the 3 3.6 V range. 2 The ADV7123-EP exhibits high performance when operating with an internal voltage reference DAC-to-DAC crosstalk is measured by holding one DAC high while the other two DACs are making low-to-high and high-to-low transitions. ...
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... ADV7123-EP CLOCK DIGITAL INPUTS ( B0, SYNC, BLANK) ANALOG INPUTS (IOR, IOR, IOG, IOG, IOB, IOB) NOTES t 1. OUTPUT DELAY ( ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT 6 OF FULL-SCALE TRANSITION OUTPUT RISE/FALL TIME ( ) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION. ...
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... GND − section of this specification is not implied. Exposure to absolute −55°C to +105°C maximum rating conditions for extended periods may affect −65°C to +150°C device reliability. 150°C 300°C 220°C ESD CAUTION Rev Page ADV7123-EP ...
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... Compensation Pin for the Internal Reference Amplifier. A 0.1 μF ceramic capacitor must be connected between COMP and Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). The V REF to V through a 0.1 μF capacitor. However, the ADV7123-EP can be overdriven by an external 1.23 V reference AA (AD1580), if required PIN 1 G1 ...
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... The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC is tied permanently low. 38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7123-EP when this pin is active. EP Exposed Pad The exposed paddle on the underside of the package must be soldered to the ground plane to increase the reliability of the solder joints and to maximize the thermal capability of the package ...
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... ADV7123-EP OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADV7123SCP170EP-RL −55°C to +105°C 1 Available in 3.3 V version only. 7.00 0.30 BSC SQ 0.23 0. 0.50 BSC EXPOSED PAD 25 24 0.45 TOP VIEW BOTTOM VIEW 0.40 0.35 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. Figure 4. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ × ...
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... NOTES Rev Page ADV7123-EP ...
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... ADV7123-EP NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09200-0-7/10(0) Rev Page ...