ad840sq Analog Devices, Inc., ad840sq Datasheet
ad840sq
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ad840sq Summary of contents
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FEATURES Wideband AC Performance Gain Bandwidth Product: 400 MHz (Gain Fast Settling: 100 ns to 0.01% for Step Slew Rate: 400 V/ s Stable at Gains Greater Full Power Bandwidth: 6.4 MHz for ...
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AD840–SPECIFICATIONS Model Conditions 1 INPUT OFFSET VOLTAGE T –T MIN Offset Drift INPUT BIAS CURRENT T –T MIN INPUT OFFSET CURRENT T –T MIN INPUT CHARACTERISTICS Differential Mode Input Resistance Input Capacitance INPUT VOLTAGE RANGE Common Mode = 10 V ...
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... C/W Recommended Heat Sink: Aavid Engineering© #602B ORDERING GUIDE Models Package Options AD840JN N-14 AD840KN N-14 AD840JQ Q-14 AD840KQ Q-14 AD840SQ Q-14 AD840SQ-883B Q-14 5962-89640012A Q-14 AD840SE-883B E-20A 5962-8964001CA E-20A NOTES 1 J and S Grade Chips also available Plastic DIP Cerdip LCC (Leadless 2 Ceramic Chip Carrier). REV +25 C ...
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AD840–Typical Characteristics Figure 1. Input Common-Mode Range vs. Supply Voltage Figure 4. Quiescent Current vs. Supply Voltage Figure 7. Quiescent Current vs. Temperature (at +25 C and unless otherwise noted) S Figure 2. Output Voltage Swing ...
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Figure 10. Open-Loop Gain and Phase Margin Phase vs. Frequency Figure 13. Common-Mode Rejection vs. Frequency Figure 16. Harmonic Distortion vs. Frequency REV. C Figure 11. Open-Loop Gain vs. Supply Voltage Figure 14. Large Signal Frequency Response Figure 17. Input ...
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AD840 Figure 19a. Inverting Amplifier Configuration (DIP Pinout) Figure 20a. Noninverting Amplifier Configuration (DIP Pinout) Figure 21. Offset Nulling (DIP Pinout) Figure 19b. Inverter Large Signal Pulse Response Figure 20b. Noninverting Large Signal Pulse Response OFFSET NULLING The input offset ...
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AD840 SETTLING TIME Figures 22 and 24 show the settling performance of the AD840 in the test circuit shown in Figure 23. Settling time is defined as: The interval of time from the application of an ideal step function input ...
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AD840 HIGH SPEED DAC BUFFER CIRCUIT The AD840’s 100 ns settling time to 0.01% for step makes it well suited as an output buffer for high speed D/A con- verters. Figure 25 shows the connections for producing ...