wms7204 Winbond Electronics Corp America, wms7204 Datasheet

no-image

wms7204

Manufacturer Part Number
wms7204
Description
256-tap Quad-channel Non-volatile Digital Potentiometer
Manufacturer
Winbond Electronics Corp America
Datasheet
PRELIMINARY
WMS7204
256-TAP QUAD-CHANNEL NON-VOLATILE DIGITAL
POTENTIOMETER
Publication Release Date: January 2003
- 1 -
Revision 1.0

Related parts for wms7204

wms7204 Summary of contents

Page 1

... QUAD-CHANNEL NON-VOLATILE DIGITAL POTENTIOMETER WMS7204 Publication Release Date: January 2003 - 1 - PRELIMINARY Revision 1.0 ...

Page 2

... SPI interface. Upon powerup the content of the NVMEM0 is automatically loaded to the Tap Register. The WMS7204 contains four independent channels in 20-pin PDIP, SOIC and TSSOP packages and can operate over a wide operating voltage range from 2.7V to 5.5V. A selectable output buffer is built- in for each channel for those applications where an output buffer is required ...

Page 3

... Power on/Preset Mem Tap bit Addressable Preset Tap bit NV Memory Power on/Preset Mem Tap bit Addressable Preset Tap bit Publication Release Date: January 2003 - 3 - WMS7204 VA1 VW1 VB1 VA2 VW2 VB2 VA3 VW3 VB3 VA4 VW4 VB4 GND V SS Revision 1.0 ...

Page 4

... Programming Non-Volatile Memory (NVMEM)..................................................................... 16 7.8.5 Reading Tap Registers and NVMEM Locations ................................................................... 17 8. TIMING DIAGRAMS.......................................................................................................................... 18 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21 10.1 Test Circuits............................................................................................................................... 23 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 24 11.1. Layout Considerations .............................................................................................................. 27 12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 28 13. ORDERING INFORMATION........................................................................................................... 31 14. VERSION HISTORY ....................................................................................................................... WMS7204 ...

Page 5

... VW2 7 14 VW4 VA2 8 13 VB4 VA3 9 12 VB3 VW3 PDIP SOIC Publication Release Date: January 2003 - 5 - WMS7204 TSSOP Revision 1.0 ...

Page 6

... Serial Clock pin. Data Shifts in one bit at a time on positive clock (CLK) edges Chip Select pin. When CS is HIGH, WMS7204 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables WMS7204, placing it in the active power mode ...

Page 7

... A terminal of potentiometer ‘4’, equivalent to the HI terminal connection on a mechanical potentiometer. B terminal of potentiometer ‘4’, equivalent to the LO terminal connection on a mechanical potentiometer. Wiper terminal of potentiometer ‘4’, equivalent to the wiper terminal of a mechanical potentiometer WMS7204 Publication Release Date: January 2003 Revision 1.0 ...

Page 8

... The chip can store four 9-bit words in nonvolatile memory (NVMEM0 ~ NVMEM3) and the word stored in the NVMEM0 will be used to set the tap register values when the device is powered up. The WMS7204 is controlled by a serial SPI interface that allows setting tap register values as well as storing data in the nonvolatile memory. ...

Page 9

... After sending one of those commands, the polled to determine when the device is ready to accept the additional data. This flow control can be used on all commands without any performance penalty although it is only needed on the commands listed above. (NVMEM not being used WMS7204 5. Therefore pin ...

Page 10

... Command and data for device 1 is shifted into device 1. Now Device 1 and 2 are correctly set up Device Command 2 FIGURE 4 – DAISY CHAIN COMMAND EXAMPLE CS CS CLK CLK SDI SDO SDI SDO Device Device Data 2 Data 2 Device xx xx Data 1 Data 1 Device Command A Data 2 Data - 10 - WMS7204 CLK SDI SDO Device xx 2 ...

Page 11

... ERIAL ATA NTERFACE The WMS7204 contains a four-wire SPI interface: SDO (Serial Data Output) Used for reading out the internal register contents and for daisy x chaining multiple devices. x SDI (Serial Data Input) Used for clocking in commands and potentiometer settings. CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled x HIGH to signal the end of the command ...

Page 12

... FIGURE 5 – SPI COMMAND WAVEFORMS - 12 - WMS7204 [ taken HIGH after command is sent ...

Page 13

... Note: C3-C0 are the command op-code; A3, A2 are the NVMEM address; A1, A0 are the channel address. 7. ASIC PERATION This chapter describes the sequences of commands to send to the WMS7204 and how to use the different features. TABLE 5 – INSTRUCTION SET Data Byte 1 D15 D14 D13 D12 D11 D10 D9 D8 ...

Page 14

... TABLE 6 – POWER RELATED COMMANDS Data Byte WMS7204 Data Byte 2 Comment Wake Up entire chip Send chip into power save ...

Page 15

... The only way to change the output buffer mode is to write the desired value of bit D8 into an NVMEM location and then load the corresponding NVMEM location into the tap register. Publication Release Date: January 2003 - 15 - WMS7204 Revision 1.0 ...

Page 16

... Non-Volatile Memory (NVMEM) TABLE 8 – PROGRAMMING NVMEM Data Byte WMS7204 Data Byte 2 Comment Writes a value to the tap register of the selected channel ...

Page 17

... Publication Release Date: January 2003 - 17 - WMS7204 Comment Read the value of the selected NVMEM location Read the value of the ...

Page 18

... TIMING DIAGRAMS CLK t LEAD CS t DSU MSB SDI t LAC MSB SDO t RSU R/B t WPSU WP FIGURE 6 – WMS7204 TIMING DIAGRAM t t CYC WMS7204 LAG LSB t LRL LSB WPH ...

Page 19

... TABLE 10 – TIMING PARAMETERS SYMBOL t CYC LEAD t LAG t DSU LAC t LRL RSU WPSU t WPH - 19 - WMS7204 MIN. MAX. UNIT 100 100 ns 100 500 600 ns 0 Publication Release Date: January 2003 Revision 1 ...

Page 20

... TABLE 11 – ABSOLUTE MAXIMUM RATINGS Condition Junction temperature Storage temperature Voltage applied to any pad Note: Exposure to conditions beyond those listed under: Absolute Maximum Ratings, may adversely affect the life and reliability of the device. 150ºC -65º to +150ºC (V – 0.3V -0 WMS7204 Value + 0.3V) DD ...

Page 21

... 1.5 10K BW 300 50K BW 200 100K OUT Rout 1 THD V 0. WMS7204 : 2.7V~5.5V; Temp: –40°C~85°C) DD MAX. UNITS CONDITIONS +20 % T=25º LSB +1 LSB ppm =5V, DD 100 Ÿ I Total V =2.7V, DD Ÿ 120 I Total ...

Page 22

... OUT V 2 DDR I 1 DDW I 0 0.1 SB PSRR = +2.7V to 5.5V WMS7204 + ,Vin =5V 1Mhz DD pF Code = 80h V =5V 1Mhz DD pF Code = 80h 5.5 V All ops except 1.8 mA NVMEM program During Non volatile memory program ...

Page 23

... Gain vs. frequency test circuit FIGURE 7 – TEST CIRCUITS - 23 - WMS7204 10 PSRR(dB) = 20LOG ( PSS(%/% ) = ' WMS7204 WMS7204 + OUT 2.5V DC Offset WMS7204 + OUT V B Publication Release Date: January 2003 Revision 1.0 ) ...

Page 24

... FIGURE 8 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7204 (1+ ) OUT (256  256 R = Total resistance of potentiometer Wiper setting for WMS7204 FIGURE 9 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7204 AMP + 256 AMP ...

Page 25

... SDO 3 18 SDI VA1 VW1 5 16 VSS VB1 6 15 R/B VB2 7 14 VA4 VW2 8 13 VW4 VA2 9 12 VB4 VA3 10 11 VB3 VW3 C1 WMS7204P-20 FIGURE 11 – WMS7204 AUDIO TONE CONTROL - REF = 5. Publication Release Date: January 2003 WMS7204 U2 6 Revision 1.0 ...

Page 26

... Vin CONTROL 1/4 WMS7204 1 CS\ 2 CLK 3 SDI 4 WP\ 5 FIGURE 12 – PROGRAMMABLE LOW-PASS FILTER 1/4 WMS7204 20 VDD 19 SDO 6 R/B\ VSS - 26 - WMS7204 3 Vout - Title WMS7204 EXA ...

Page 27

... Sensitive traces should not run under the device or close to the bypass capacitors. A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals. pin is recommended for best performance. DD pins. Care should be taken to separate the analog and digital traces. SS FIGURE 13 – WMS7204 LAYOUT - 27 - WMS7204 Publication Release Date: January 2003 Revision 1.0 ...

Page 28

... FIGURE 14 – 20L PDIP – 300MIL - 28 - WMS7204 é A Max 3.43 0.56 1.63 0.36 7.87 6.48 2.79 3.56 15 9.53 1.91 ...

Page 29

... T FIGURE 15 – 20L SOIC – 150MIL - 29 - WMS7204 Publication Release Date: January 2003 Revision 1.0 ...

Page 30

... FIGURE 16 – 20L TSSOP – 4.4MM - 30 - WMS7204 ...

Page 31

... Single channel with SPI Interface x 02: Dual channels with SPI Interface x 04: Quad channels with SPI Interface End-to-end Resistance: x 010: 10K: x 050: 50K: x 100: 100K: Package Index TSSOP x S: SOIC x P: PDIP x M: MSOP* Publication Release Date: January 2003 - 31 - WMS7204 Revision 1.0 ...

Page 32

... FAX: 1-408-5441797 http://www.winbond-usa.com/ Winbond Electronics Corporation Japan 7F Daini-ueno BLDG. 3-7-18 Shinyokohama Kohokuku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 32 - WMS7204 DESCRIPTION Winbond Electronics (Shanghai) Ltd. 27F, 299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62356998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...

Related keywords