hi5960 Intersil Corporation, hi5960 Datasheet
hi5960
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hi5960 Summary of contents
Page 1
... Data Sheet 14-Bit, 130MSPS, High Speed D/A Converter The HI5960 is a 14-bit, 130MSPS (Mega Samples Per Second), high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge- triggered CMOS input data latches ...
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... LATCH D10 D11 D12 (MSB) D13 CLK AV ACOM DV DCOM HI5960 HI5960 (25) ACOM D13 D13 (1) (15) SLEEP D12 D12 (2) (16) REFLO D11 D11 (3) D10 D10 (4) (17) REFIO (7) (18) FSADJ (9) ...
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... DD 28 CLK 3 HI5960 Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. Connect to analog ground to enable internal 1.2V reference or connect to AV reference ...
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... OUT Operating Conditions HI5960IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... Spurious Free Dynamic Range, f CLK SFDR Within a Window f CLK +3V Power Supply f CLK Total Harmonic Distortion (THD CLK Nyquist f CLK 5 HI5960 = DV = +5V Internal 1.2V, IOUTFS = 20mA REF TEST CONDITIONS = 100MSPS 4.0MHz (Notes 4, 8) OUT = 50MSPS 2.0MHz (Notes 4, 8) OUT = 25MSPS 1.0MHz (Notes 4, 8) OUT = 130MSPS ...
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... Data Hold Time, t See Figure 4 (Note 3) HLD Propagation Delay Time, t See Figure 4 PD CLK Pulse Width See Figure 4 (Note 3) PW1 PW2 6 HI5960 = DV = +5V Internal 1.2V, IOUTFS = 20mA REF TEST CONDITIONS = 130MSPS 40.4MHz (Notes 4, 8) OUT = 130MSPS 10.1MHz (Notes 4, 8) OUT = 130MSPS ...
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... Measured with the clock at 130MSPS and the output frequency at 10MHz. 8. See “Definition of Specifications” recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V not have to be equal. 7 HI5960 = DV = +5V Internal 1.2V, IOUTFS = 20mA REF ...
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... Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. Detailed Description The HI5960 is a 14-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 130MSPS and can be powered by either single or dual power supplies in the or T ...
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... DAC is set to 20mA THE IMPEDANCE EQ LOADING EACH OUTPUT HI5960 V OUT will equal center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. Since the DAC’s output voltage compliance range is - ...
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... SETT t PD FIGURE 2. OUTPUT SETTLING TIME DIAGRAM CLK t SU D13-D0 I OUT t PD FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 10 HI5960 50% ERROR BAND FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT t t PW1 PW2 HLD HLD t SETT ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. 11 HI5960 M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 HI5960 M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE ...