adsp-2185m Analog Devices, Inc., adsp-2185m Datasheet
adsp-2185m
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adsp-2185m Summary of contents
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... MEMORY MEMORY 16K 24 BIT 16K 16 BIT PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA SERIAL PORTS SPORT0 SPORT1 SHIFTER Microcomputer ADSP-2185M FULL MEMORY MODE PROGRAMMABLE EXTERNAL I/O ADDRESS AND BUS FLAGS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL ...
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... Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IACK Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . 12 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory Mapped Registers (New to the ADSP-2185M I/O Space (Full Memory Mode Composite Memory Select (CMS Byte Memory Select (BMS Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Byte Memory DMA (BDMA, Full Memory Mode Internal Memory DMA Port (IDMA Port ...
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... Every instruction can execute in a single processor cycle. The ADSP-2185M’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel. In one processor cycle, the ADSP-2185M can: • Generate the next program address • Fetch the next instruction • ...
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... Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permit- ting the ADSP-2185M to fetch two operands in a single cycle, one from program memory and one from data memory. The ADSP-2185M can fetch an operand from program memory and the next instruction in the same cycle ...
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... The ADSP-2185M incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2185M SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section ...
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... ADSP-2185M Common-Mode Pins Pin Name # of Pins RESET BGH 1 DMS 1 PMS 1 IOMS 1 BMS 1 CMS IRQ2 1 PF7 IRQL1 1 PF6 IRQL0 1 PF5 IRQE 1 PF4 Mode D 1 PF3 Mode C 1 PF2 Mode B 1 PF1 Mode A 1 PF0 CLKIN, XTAL 2 CLKOUT 1 SPORT0 ...
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... Memory Interface Pins The ADSP-2185M processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full exter- nal overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. ...
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... ADSP-2185M Terminating Unused Pins The following table shows the recommendations for terminating unused pins. Pin Terminations I/O 3-State Reset Pin Name (Z) State XTAL I I CLKOUT O O A13 (Z) Hi-Z IAD 12:0 I/O (Z) Hi (Z) Hi-Z D23:8 I/O (Z) Hi I/O (Z) Hi-Z IWR I/O (Z) Hi-Z IRD I/O (Z) Hi-Z IAL ...
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... Power-down acknowledge pin indicates when the processor has entered power-down. Idle When the ADSP-2185M is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruc- tion ...
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... The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected. The ADSP-2185M uses an input clock with a frequency equal to half the instruction rate; a 37.50 MHz input clock yields processor cycle (which is equivalent to 75 MHz). Normally, instructions are executed in a single processor cycle ...
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... CLKIN XTAL DSP RESET The RESET signal initiates a master reset of the ADSP-2185M. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time ...
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... External Overlay 1 2 External Overlay 2 MEMORY ARCHITECTURE The ADSP-2185M provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to the following figures and tables for PM and DM memory allocations in the ADSP-2185M. Program Memory Program Memory (Full Memory Mode 24-bit-wide space for storing both instruction opcodes and data ...
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... Data Memory (Full Memory Mode 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2185M has 16K words on Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus ...
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... BDMA feature. The byte memory space con- sists of 256 pages, each of which is 16K × 8. The byte memory space on the ADSP-2185M supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. This allows meg × ...
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... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2185M. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...
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... BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution Mode is enabled, the ADSP-2185M will not halt program execution until it encounters an instruction that requires an external memory access. If the ADSP-2185M is performing an external memory access ...
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... The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the ADSP-2185M in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. ...
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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7 BR. 9 Idle refers to ADSP-2185M state of operation during execution of IDLE instruction. Deasserted pins are driven to either measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 12, 13, 14), 30% are Type 2 DD and Type 6, and 20% are idle instructions ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2185M features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Total power dissipation for this example is P 2°C/W 7.4°C/W Output Drive Currents Figure 14 shows typical I-V characteristics for the output drivers on the ADSP-2185M. The curves represent the current drive capability of the output drivers as a function of output voltage –20 – ...
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... ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. 4 IDLE REFERS TO STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V OR GND. Capacitive Loading Figure 16 and Figure 17 show the capacitive loading character- 110mW istics of the ADSP-2185M. 30 95mW 25 82mW ...
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... ADSP-2185M TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time ( the difference of t DIS MEASURED in the Output Enable/Disable diagram ...
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... Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time). CLKIN CLKOUT PF(3:0) RESET Min 26 0.5t – 0.5t – CKI t CKIH t CKIL t CKOH t CKH t CKL RSP PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A ADSP-2185M Max Unit ...
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... ADSP-2185M Parameter Interrupts and Flags Timing Requirements: IRQx, FI, or PFx Setup before CLKOUT Low t IFS IRQx, FI, or PFx Hold after CLKOUT High t IFH Switching Characteristics: t Flag Output Hold after CLKOUT Low FOH t Flag Output Delay from CLKOUT Low FOD NOTES 1 If IRQx and FI inputs meet t and t setup/hold requirements, they will be recognized during the current clock cycle ...
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... BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. CLKOUT BR CLKOUT PMS, DMS BMS BGH Min 1 0.25t 1 0.25t 0 0 0.25t SDB t SDBH ADSP-2185M Max + 0.25t + 8 CK – SEC SEH Unit ...
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... ADSP-2185M Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, xMS Setup before RD Low t ASR A0–A13, xMS Hold after RD Deasserted t RDA ...
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... CK 0 0.25t – 0.25t – 0.25t – 0.75t – 0.25t – 0.5t – WRA WWR ASW CWR WDE ADSP-2185M Max Unit 0. DDR ...
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... ADSP-2185M Serial Ports Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLKIN Width SCP Switching Characteristics: t CLKOUT High to SCLKOUT CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...
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... Start of Write or Read = IS Low and IWR Low or IRD Low. IACK IAL IS IAD15–0 IRD OR IWR Min IKA t IALD t t IALP IALP t t IASU IASU t IAH ADSP-2185M Max Unit IAH t IALS ...
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... ADSP-2185M Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristic: Start of Write to IACK High ...
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... This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. IACK IS IWR IAD15–0 Min 0. 1. IDSU IDH , t . IKSU IKH t IKW t IKHW t IKLW t IKSU DATA ADSP-2185M Max + IKH Unit ...
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... ADSP-2185M Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR End of read after IACK Low t IRK Switching Characteristics: IACK High after Start of Read t IKHR IAD15–0 Data Setup before IACK Low t IKDS t IAD15–0 Data Hold after End of Read ...
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... Second half of PM Read. 6 End of Read = IS High or IRD High IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS IAD15–0 DATA t IRDV ADSP-2185M Min Max – – IKDH t IKDD Unit ...
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... ADSP-2185M Parameter IDMA Read, Short Read Cycle in Short Read Only Mode Timing Requirements: IACK Low before Start of Read t IKR 3 t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Previous Data Hold after End of Read IKDH t IAD15–0 Previous Data Disabled after End of Read ...
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... PMS 23 IOMS 24 CMS TOP VIEW ADSP-2185M D15 D14 D13 D12 GND D11 D10 D9 V DDEXT GND D8 D7/IWR D6/IRD D5/IAL D4/IS GND V DD INT D3/IACK D2/IAD15 D1/IAD14 D0/IAD13 BG EBG BR EBR ...
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... ADSP-2185M The LQFP package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...
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... D6/IRD D2/IAD15 TFS0 DT0 V DDINT D0/IAD13 SCLK0 V RFS1/IRQ0 DDEXT DMS SCLK1 RFS0 TFS1/IRQ1 PMS GND DR0 GND GND DR1/FI DT1/FO GND ADSP-2185M GND A1/IAD0 A2/IAD1 NC GND A3/IAD2 A4/IAD3 A5/IAD4 RD A6/IAD5 PWDACK BGH FL0 A8/IAD7 V V DDEXT DDEXT ...
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... ADSP-2185M The Mini-BGA package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. ...
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... TYP 100 12 0.50 1 TYP SEATING PLANE TOP VIEW (PINS DOWN) 0.08 25 MAX LEAD 26 6 ± 4 COPLANARITY 0 – 7 0.50 BSC 0.15 LEAD PITCH 0.05 NOTE: THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. ADSP-2185M 0.27 0.22 TYP 0.17 LEAD WIDTH ...
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... ADSP-2185MBST-266 –40°C to +85°C ADSP-2185MKCA-300 0°C to 70°C ADSP-2185MBCA-266 –40°C to +85°C In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labeled TQFP packages (1.6 mm thick) are now designated as LQFP. OUTLINE DIMENSIONS Dimensions shown in millimeters ...