adsp-21363sksqzeng Analog Devices, Inc., adsp-21363sksqzeng Datasheet
adsp-21363sksqzeng
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adsp-21363sksqzeng Summary of contents
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... On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21363 is available with a 333 MHz core instruction rate. For complete ordering information, see Guide on Page 44 BLOCK 0 ...
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... ADSP-21363 KEY FEATURES – PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-21363 performs 2 GFLOPS/666 MMACS 3M bit on-chip single-ported SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit in blocks 2 and 3) for simultaneous access by the core processor and DMA 4M bit on-chip mask-programmable ROM (2M bit in block 0 ...
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... Preliminary Technical Data GENERAL DESCRIPTION The ADSP-21363 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices' Super Har- vard Architecture. The ADSP-21363 is source code compatible with the ADSP-2126x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (Sin- gle-Instruction, Single-Data) mode ...
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... Fourier transforms. The two DAGs of the ADSP-21363 contain sufficient registers to allow the creation circular buff- ers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation ...
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... I/O processor single cycle. The ADSP-21363’s, SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to three megabits ...
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... IDP (Input Data Port), the Parallel Data Acquisition Port (PDAP), or the parallel port. Twenty-five channels of DMA are available on the ADSP-21363—two for the SPI interface, two for memory-to-memory transfers, twelve via the serial ports, eight via the Input Data Port, and one via the processor’s parallel port ...
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... PWM patterns that produce lower harmonic distortion in three-phase PWM inverters. Timers The ADSP-21363 has a total of four timers: a core timer able to generate periodic software interrupts and three general purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: • ...
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... Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21363 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG ...
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... EZ-KIT Lite board enables high-speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21363 architecture and functionality. For detailed information on the ADSP-2136x Family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference ...
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... Open Drain, and T = Three-State , (pd) = pulldown resistor, (pu) = pullup resistor. Function Parallel Port Address/Data. The ADSP-21363 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode ...
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... MOSI input(s) of the slave(s). MOSI has a 22.5 k: internal pullup resistor. SPI Master In Slave Out. If the ADSP-21363 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21363 is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data ...
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... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21363. TRST has a 22.5 k: internal pullup resistor. Emulation Status. Must be connected to the ADSP-21363 Analog Devices DSP Tools product line of JTAG emulators target board connector only ...
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... Table 7. Address/ Data Mode Selection EP Data ALE Mode 8-bit Asserted 8-bit Deasserted 16-bit Asserted 16-bit Deasserted Rev. PrA | Page September 2004 ADSP-21363 Timing Specifications 16. Core to CLKIN Ratio 6:1 32:1 16:1 AD7–0 AD15–8 Function Function A15–8 A23–16 D7–0 A7–0 A7– ...
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... ADSP-21363 ADSP-21363 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V IH_CLKIN V Low Level Input Voltage @ V ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21363 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... ADSP-21363 Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control Table 8. ADSP-21363 CLKOUT and CCLK Clock Generation Operation Timing Description Requirements CLKIN Input Clock CCLK Core Clock Table 9. Clock Periods 1 Timing Description Requirements t CLKIN Clock Period ...
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... Table 12. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097 t RSTVDD t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 6. Power Up Sequencing Rev. PrA | Page September 2004 ADSP-21363 Min Max 0 –50 200 0 200 4096t ...
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... CK CLKIN t CKH Figure 7. Clock Input Clock Signals The ADSP-21363 can use an external clock or a crystal. See CLKIN pin description in Table 3 on Page can configure the ADSP-21363 to use its internal clock genera- tor by connecting the necessary components to CLKIN and XTAL. Figure 8 shows the component connections used for a crystal operating in fundamental mode ...
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... Table 13. Interrupts Parameter Timing Requirement t IRQx Pulse Width IPW DAI_P20-1 FLAG2-0 (IRQ2-0) Min WRST Figure 9. Reset Min 2 × t PCLK t IPW Figure 10. Interrupts Rev. PrA | Page September 2004 ADSP-21363 Max Unit SRST Max Unit + 2 ns ...
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... ADSP-21363 Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer (CTIMER). Table 14. Core Timer Parameter Switching Characteristic t CTIMER Pulse Width WCTIM FLAG3 (CTIMER) Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0, Timer1, and Timer2 in PWM_OUT (pulse width modulation) mode. ...
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... Delay DAI Pin Input Valid to DAI Output Valid DPIO Min 2 t PCLK t PWI Figure 13. Timer Width Capture Timing Min 1.5 DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin to PIN Direct Routing Rev. PrA | Page September 2004 ADSP-21363 Max Unit 31 2(2 – PCLK Max Unit 10 ns ...
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... ADSP-21363 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the Precision Clock Generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 18 ...
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... FLAG3–0 IN Pulse Width FIPW Switching Characteristic t FLAG3–0 OUT Pulse Width FOPW DAI_P20-1 (FLAG3-0 DAI_P20-1 (FLAG3-0 (AD15-0) for ) IN (AD15-0) t FIPW ) OUT t FOPW Figure 16. Flags Rev. PrA | Page September 2004 ADSP-21363 Min Max Unit 2 × PCLK 2 × t – PCLK ...
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... ADSP-21363 Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21363 is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
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... RRH RDDRV t ALEHZ t t DRS t t DRH ADAS ADAH VALID ADDRESS VALID DATA Figure 18. Read Cycle For 16-Bit Memory Timing Rev. PrA | Page September 2004 ADSP-21363 Min Max Unit 3 × t – PCLK t – 2.5 ns PCLK 2 × t – 2 ...
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... ADSP-21363 Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21363 is accessing external memory space. Table 22. 8-bit Memory Write Cycle Parameter Switching Characteristics: t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ...
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... ALERW WRH DWH ADAS ADAH VALID VALID DATA ADDRESS t DWS Figure 20. Write Cycle For 16-Bit Memory Timing Rev. PrA | Page September 2004 ADSP-21363 Min Max Unit 2 × t – PCLK t – 2.5 ns PCLK 2 × t – PCLK – ...
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... ADSP-21363 Serial Ports To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width. Table 24. Serial Ports—External Clock ...
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... SFSE/I HFSE DDTENFS t HDTE/I 1ST BIT t DDTLFSE DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P20-1 PINS 1 Figure 21. External Late Frame Sync Rev. PrA | Page September 2004 ADSP-21363 Max Unit Max Unit DDTE/I 2ND BIT DDTE/I 2ND BIT ...
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... ADSP-21363 DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW DAI_P20-1 (SCLK) t DFSI t HOFSI DAI_P20-1 (FS) DAI_P20-1 (DATA CHANNEL A/B) NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT — INTERNAL CLOCK DRIVE EDGE ...
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... DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. DAI_P20-1 (SCLK) DAI_P20-1 (FS) DAI_P20-1 (SDATA) Table 28.IDP Min 2.5 2.5 2.5 2 SAMPLE EDGE t SISCLKW t SISFS t SISD Figure 23. IDP Master Timing Rev. PrA | Page September 2004 ADSP-21363 Max Unit SIHFS t SIHD ...
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... The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x SHARC Processor Hardware Refer- Table 29. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
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... Preliminary Technical Data SPI Interface—Master The ADSP-21363 contains two SPI ports. The primary has dedi- cated pins and the secondary is available through the DAI. The timing provided in Table 30 and Table 31 Table 30. SPI Interface Protocol — Master Switching and Timing Specifications ...
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... ADSP-21363 SPI Interface—Slave Table 31. SPI Interface Protocol —Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 ...
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... TDI TDO SYSTEM INPUTS SYSTEM OUTPUTS Min TCK t t STAP HTAP t DTDO t DSYS Figure 27. IEEE 1149.1 JTAG Test Access Port Rev. PrA | Page September 2004 ADSP-21363 Max Unit SSYS HSYS ...
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... ADSP-21363 OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output driv- ers of the ADSP-21363. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125° -10 3.11V, 125° -30 3.47V, -45° ...
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... LOAD CAPACITANCE (pF) Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21363 processor is rated for performance to a maxi- mum junction temperature of 125°C. Table 33 through Table 36 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... ADSP-21363 Table 36. Thermal Characteristics for 144-Lead Integrated Heatsink (INT–HS) LQFP (With heat slug soldered to PCB) Parameter Condition Airflow = 0 m Airflow = 1 m/s T JMA Airflow = 2 m/s T JMA T JC < Airflow = 0 m/s JT Airflow = 1 m/s < JMT Airflow = 2 m/s < JMT 1 The thermal characteristics values provided in these tables are modeled values. ...
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... B14 F01 AD7 F02 V DDINT F04 V DDEXT F05 DAI_P19 (SCLK45) F06 F09 F10 F11 F13 F14 Rev. PrA | Page September 2004 ADSP-21363 BGA Pin Name BGA Pin# Pin# C01 V D01 DDINT C02 GND D02 C03 GND D04 C12 GND D05 ...
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... ADSP-21363 Table 37. 136-Ball Mini-BGA Pin Assignments (Continued) Pin Name BGA Pin Name Pin# AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) ...
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... KEY V A GND* DDINT VDD V A I/O SIGNALS DDEXT VSS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Rev. PrA | Page September 2004 ADSP-21363 ...
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... ADSP-21363 144-LEAD LQFP PIN CONFIGURATIONS The following table shows the ADSP-21363’s pin names and their default function after reset (in parentheses). Table 38. 144-Lead LQFP Pin Assignments Pin Name LQFP Pin Name Pin No DDINT DDINT CLKCFG0 2 GND CLKCFG1 3 RD BOOTCFG0 ...
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... Preliminary Technical Data PACKAGE DIMENSIONS The ADSP-21363 is available in a 136-ball Mini-BGA package and a 144-lead integrated heatsink LQFP package. 0.27 0.22 TYP 0.17 SEATING PLANE 0.08 MAX (LEAD COPLANARITY) 0. 0.60 TYP 1. 35 0.45 1.60 MAX DE TAIL A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-026-BFB-HD. 2. ACTUAL PO SITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTI ON ...
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... OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. 4. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR THE BALL DIAMETER. 5. CENTER DIMENSIONS ARE NOMINAL. ORDERING GUIDE Part Number Ambient Temperature Range qC ADSP-21363SKBCZENG ADSP-21363SKBC-ENG ADSP-21363SKSQZENG ADSP-21363SKSQ-ENG ADSP-21363SBBCZENG – ADSP-21363SBBC-ENG – ADSP-21363SBSQZENG – ADSP-21363SBSQ-ENG – ...