adsp-21371 Analog Devices, Inc., adsp-21371 Datasheet
adsp-21371
Available stocks
Related parts for adsp-21371
adsp-21371 Summary of contents
Page 1
... On-chip memory—1M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21371 is available with a 266 MHz core instruction rate with unique audiocentric peripherals such as the digi- tal applications interface, serial ports, precision clock generators, and more ...
Page 2
... ADSP-21371 KEY FEATURES PROCESSOR CORE — At 266 MHz (3.75 ns) core instruction rate, the ADSP-21371 performs 1.596 GFLOPs/533 MMACs 1M bit on-chip, SRAM for simultaneous access by the core processor and DMA 4M bit on-chip, mask-programmable ROM Dual data address generators (DAGs) with modulo and bit- ...
Page 3
... TABLE OF CONTENTS Summary ................................................................1 Key Features—Processor Core ..................................2 Input/Output Features ............................................2 General Description ..................................................4 ADSP-21371 Family Core Architecture .......................4 ADSP-21371 Memory .............................................5 External Memory ...................................................5 ADSP-21371 Input/Output Features ...........................7 System Design ..................................................... 10 Development Tools .............................................. 10 Additional Information ......................................... 11 Pin Function Descriptions ........................................ 12 Data Modes ........................................................ 14 Boot Modes ........................................................ 14 Core Instruction Rate to CLKIN Ratio Modes ............. 14 ADSP-21371 Specifications ...
Page 4
... ADSP-21371 GENERAL DESCRIPTION The ADSP-21371 SHARC processor is a member of the SIMD SHARC family of DSPs that feature Analog Devices' Super Har- vard Architecture. The ADSP-21371 is source code compatible with the ADSP-2126x, ADSP-2136x, and ADSP-2116x DSPs as well as with first generation ADSP-2106x SHARC processors in SISD (single-instruction, single-data) mode ...
Page 5
... I/O processor single cycle. The ADSP-21371’s SRAM can be configured as a maximum of 32k words of 32-bit data, 64k words of 16-bit data, 21.3k words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes megabit ...
Page 6
... ADSP-21371 Table 2. ADSP-21371 Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 bits) Instruction Word (48 bits) BLOCK 0 ROM BLOCK 0 ROM 0x0004 0000–0x0004 7FFF 0x0008 0000–0x0008 AAA9 Reserved Reserved 0x0004 8000–0x0004 BFFF 0x0008 AAAA–0x0008 FFFF ...
Page 7
... IDP (input data port), the parallel data acquisition port (PDAP) or the UART. Thirty-two channels of DMA are available on the ADSP-21371, 16 via the serial ports, eight via the input data port, two for the UART, two for the SPI interface, two for the external port, and two for memory-to-memory transfers ...
Page 8
... The DAI also includes eight serial ports, four precision clock generators (PCG), and an input data port (IDP). The IDP pro- vides an additional input path to the ADSP-21371 core, configurable as either eight channels of I gle 20-bit wide synchronous parallel data acquisition port. Each data channel has its own DMA channel that is independent from the ADSP-21371’ ...
Page 9
... In conjunction with the general-purpose timer functions, auto- baud detection is supported. Timers The ADSP-21371 has a total of three timers: a core timer that can generate periodic software interrupts and two general pur- pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
Page 10
... Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21371 pro- cessor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG ...
Page 11
... EZ-KIT Lite board enables high speed, non- intrusive emulation. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21371 architecture and functionality. For detailed information on the ADSP-2137x family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Programming Reference. ...
Page 12
... External Port Read Enable asserted whenever the ADSP-21371 reads a word from driven high external memory. RD has a 22.5 k: internal pull-up resistor. Pulled high/ External Port Write Enable asserted when the ADSP-21371 writes a word to driven high external memory. WR has a 22.5 k: internal pull-up resistor. Pulled high/ SDRAM Row Address Strobe. Connect to SDRAM’ ...
Page 13
... ADSP-21371. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21371. TRST has a 22.5 k: internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21371 Analog Devices DSP Tools product line of JTAG emulators target board connector only ...
Page 14
... ADSP-21371 DATA MODES The upper 32 data pins of the external memory interface are muxed (using bits in the SYSCTL register) to support the exter- nal memory interface data (input/output), the PDAP (input only), and the FLAGS (input/output). Table 6 settings. Table 6. Function of Data Pins DATA PIN MODE ...
Page 15
... ADSP-21371 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DDINT V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V IH_CLKIN 3 V Low Level Input Voltage @ V IL_CLKIN T Junction Temperature 208-Lead MQFP @ T ...
Page 16
... ADSP-21371 PACKAGE INFORMATION The information presented in Figure 2 the package branding for the ADSP-21371 processor. For a complete listing of product availability, see Page 48. a ADSP-2137x tppZ-cc vvvvvv.x n.n yyww country_of_origin S Figure 2. Typical Package Brand Table 9. Package Brand Information Brand Key Field Description t Temperature Range ...
Page 17
... TIMING SPECIFICATIONS The ADSP-21371’s internal clock (a multiple of CLKIN) pro- vides the clock signal for timing internal memory, processor core, and serial ports. During reset, program the ratio between the processor’s internal clock frequency and external (CLKIN) clock frequency with the CLKCFG1–0 pins (see Page 14) ...
Page 18
... ADSP-21371 Note the definitions of various clock periods shown in which are a function of CLKIN and the appropriate ratio con- trol shown in Table 11. Table 11. ADSP-21371 CLKOUT and CCLK Clock Generation Operation Timing Requirements Description Calculation CLKIN Input Clock 1/t CCLK Core Clock 1/t Table 12. Clock Periods ...
Page 19
... Table 15. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in t RSTVDD t IVDDEVDD t CLKVDD t CLKRST t PLLRST Figure 4. Power-Up Sequencing Rev Page June 2007 ADSP-21371 Min Max 0 –50 200 0 200 4096 ...
Page 20
... CK CLKIN t CKH Figure 5. Clock Input Clock Signals The ADSP-21371 can use an external clock or a crystal. See the CLKIN pin description in Table 5. The programmer can config- ure the ADSP-21371 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. Figure 6 shows the component connections used for a crystal operating in fundamental mode ...
Page 21
... Running RESET Pulse Width Low WRUNRST t Running RESET Setup Before CLKIN High SRUNRST CLKIN RUNRSTIN Min RUNWRST RUNSRST Figure 7. Reset Min SRUNRST t WRUNRST Figure 8. Running Reset Rev Page June 2007 ADSP-21371 Max Unit ns ns Max Unit ns ns ...
Page 22
... ADSP-21371 Interrupts The following timing specification applies to the FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts as well as the DAI_P20-1 and DPI_P14-1 pins when they are configured as interrupts. Table 17. Interrupts Parameter Timing Requirement t IRQx Pulse Width ...
Page 23
... Delay DAI/DPI Pin Input Valid to DAI Output Valid DPIO Min 2 × t PCLK t PWI Figure 12. Timer Width Capture Timing Min 1.5 DAI_Pn DPI_Pn DAI_pm DPI_Pm t DPIO Figure 13. DAI Pin to Pin Direct Routing Rev Page June 2007 ADSP-21371 Max Unit 31 2 ×(2 – 1) × PCLK Max Unit 10 ns ...
Page 24
... ADSP-21371 Precision Clock Generator (Direct Pin Routing) This timing is only valid when the SRU is configured such that the precision clock generator (PCG) takes its inputs directly from the DAI pins (via pin buffers) and sends its outputs directly to the DAI pins. For the other cases, where the PCG’s Table 22 ...
Page 25
... DPI_P14-1, DATA31-0, FLAG3–0 OUT Pulse Width FOPW DPI_P14 (FLAG3 (DATA31 DPI_P14 (FLAG3 (DATA31 Table FIPW - OUT - 0) t FOPW Figure 15. Flags Rev Page June 2007 ADSP-21371 Min Max 2 × PCLK 2 × PCLK Unit ns ns ...
Page 26
... ADSP-21371 SDRAM Interface Timing (133 MHz SDCLK) 1 Table 24. SDRAM Interface Timing Parameter Timing Requirements t DATA Setup Before SDCLK SSDAT t DATA Hold After SDCLK HSDAT Switching Characteristics t SDCLK Period SDCLK t SDCLK Width High SDCLKH t SDCLK Width Low SCCLKL t Command, ADDR, Data Delay After SDCLK ...
Page 27
... SDS. Test Conditions on Page 44 for the calculation of hold times given capacitive and dc loads DRLD t DAD t DSAK Figure 17. Memory Read—Bus Master Rev Page June 2007 ADSP-21371 Max W+t –5.12 SDCLK W – –10.1+ W SDCLK W – 7.0 SDCLK or t DAAK DSAK ...
Page 28
... ADSP-21371 Memory Write Bus Master — Use these specifications for asynchronous interfacing to memo- ries. Note that timing for ACK, DATA, RD, WR, and strobe timing parameters only apply to asynchronous access mode. Table 26. Memory Write Bus Master — Parameter Timing Requirements t ACK Delay from Address, Selects ...
Page 29
... Referenced to drive edge. Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Rev Page June 2007 ADSP-21371 Min Max Unit 2 ...
Page 30
... ADSP-21371 Table 29. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 30. Serial Ports—External Late Frame Sync ...
Page 31
... HFSI SFSI - DAI_P20 1 (FS) - DAI_P20 1 (DATA CHANNEL A/B) SCLK t DDTTE Figure 19. Serial Ports Rev Page June 2007 ADSP-21371 DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE ...
Page 32
... ADSP-21371 DAI_P20 - 1 (SCLK) DAI_P20 - 1 (FS) DAI_P20 - 1 (DATA CHANNEL A/B) DAI_P20 - 1 (SCLK) DAI_P20 - 1 (FS) DAI_P20 - 1 (DATA CHANNEL A/B) NOTE: SERIAL PORT SIGNALS (SCLK, FS, USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20 THE CHARACTERIZED AC SPORT TIMINGS ARE APPLICABLE WHEN INTERNAL CLOCKS AND FRAMES ARE LOOPED BACK FROM THE PIN, NOT ROUTED DIRECTLY THROUGH SAU ...
Page 33
... DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins. DAI_P20 (SCLK) DAI_P20 DAI_P20 (SDATA) Table 31. IDP SAMPLE EDGE t IPDCLK IPDCLKW t t SISFS SIHFS - 1 (FS SISD SIHD - 1 Figure 21. IDP Master Timing Rev Page June 2007 ADSP-21371 Min Max Unit 3.8 ns 2.5 ns 2 ...
Page 34
... ADSP-21371 Parallel Data Acquisition Port (PDAP) The timing requirements for the PDAP are provided in Table 32. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the PDAP, see the PDAP chapter of the ADSP-21368 SHARC Processor Hardware Table 32. Parallel Data Acquisition Port (PDAP) ...
Page 35
... Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Min t – 2.5 PCLK 2 × t – 2.5 PCLK t PWMW t PWMP Figure 23. PWM Timing Rev Page June 2007 ADSP-21371 Max Unit 16 (2 – 2) × t – 2.5 ns PCLK 16 (2 – 1) × t – 2.5 ns PCLK ...
Page 36
... ADSP-21371 S/PDIF Transmitter Serial data input to the S/PDIF transmitter can be formatted as 2 left justified right justified with word widths of 16-, 18-, 20-, or 24-bits. The following sections provide timing for the transmitter. S/PDIF Transmitter-Serial Input Waveforms Figure 24 shows the right-justified mode. LRCLK is high for the left channel and low for the right channel ...
Page 37
... TxCLK Frequency for TxCLK = 256 × FS Frame Rate Min SITXCLKW t SITXCLK t SISCLKW t SISCLK t SISFS t SISD Figure 27. S/PDIF Transmitter Input Timing Min Rev Page June 2007 ADSP-21371 Max Unit SIHFS t SIHD Max Unit 73.8 MHz 49.2 MHz 192.0 kHz ...
Page 38
... ADSP-21371 S/PDIF Receiver The following section describes timing as it relates to the S/PDIF receiver. Internal Digital PLL Mode In the internal digital phase-locked loop mode the internal PLL (digital PLL) generates the 512 × FS clock. Table 36. S/PDIF Receiver Internal Digital PLL Mode Timing ...
Page 39
... SPI Interface—Master The ADSP-21371 contains two SPI ports. Both primary and sec- ondary are available through DPI only. The timing provided in Table 37 and Table 38 applies to both. Table 37. SPI Interface Protocol — Master Switching and Timing Specifications Parameter Timing Requirements t Data Input Valid To SPICLK Edge (Data Input Setup Time) ...
Page 40
... ADSP-21371 SPI Interface—Slave Table 38. SPI Interface Protocol — Slave Switching and Timing Specifications Parameter Timing Requirements t Serial Clock Cycle SPICLKS t Serial Clock High Period SPICHS t Serial Clock Low Period SPICLS t SPIDS Assertion to First SPICLK Edge SDSCO CPHASE = 0 CPHASE = 1 t Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0 ...
Page 41
... PCLK Min t95 t95 - DATA(5 8) STOP - DATA(5 8) STOP(1 Figure 31. UART Port—Receive and Transmit Timing Rev Page June 2007 ADSP-21371 Max Unit ns ns UART RECEIVE BIT SET BY DATA STOP; CLEARED BY FIFO READ - 2) UART TRANSMIT BIT SET BY PROGRAM; CLEARED BY WRITE TO TRANSMIT ...
Page 42
... ADSP-21371 TWI Controller Timing Table 40 and Figure 32 provide timing information for the TWI interface. Input Signals (SCL, SDA) are routed to the DPI_P14–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DPI_P14–1 pins. Table 40. Characteristics of the SDA and SCL Bus Lines for F/S-Mode TWI Bus Devices ...
Page 43
... TDO SYSTEM INPUTS SYSTEM OUTPUTS Min TCK t t STAP HTAP t DTDO t t SSYS HSYS t DSYS Figure 33. IEEE 1149.1 JTAG Test Access Port Rev Page June 2007 ADSP-21371 Max Unit ...
Page 44
... ADSP-21371 OUTPUT DRIVE CURRENTS Figure 34 shows typical I-V characteristics for the output driv- ers of the ADSP-21371. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125° 3.11V, 125° 3.47V, - 45° ...
Page 45
... LOAD CAPACITANCE (pF) Figure 39. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21371 processor is rated for performance over the temperature range specified in Operating Conditions on Page 15. Table 42 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measure- ment complies with JESD51-8 ...
Page 46
... ADSP-21371 208-LEAD MQFP PINOUT Table 43. 208-Lead MQFP Pin Assignment (Numerically by Lead Number) Pin No. Signal Pin No DDINIT 2 DATA28 54 3 DATA27 55 4 GND DDEXT 6 DATA26 58 7 DATA25 59 8 DATA24 60 9 DATA23 61 10 GND DDINT 12 DATA22 64 13 DATA21 ...
Page 47
... GND ADDR23 152 V DD ADDR22 153 GND MS1 154 V DD MS0 155 GND V 156 Rev Page June 2007 ADSP-21371 Pin No. Signal 201 CLKOUT/ ~RESETOUT/ ~RUNRSTIN 202 RESET 203 V DDEXT 204 GND 205 DATA30 206 DATA31 207 DATA29 208 V ...
Page 48
... ADSP-21371 OUTLINE DIMENSIONS The ADSP-21371 is available in a 208-lead Pb-free MQFP package. 3.60 3.40 3.20 0.50 0.25 0.08 MAX (LEAD COPLANARITY) VIEW A ROTATED 90° CCW ORDERING GUIDE Temperature 1 Model Range 2 ADSP-21371KSZ- +70 C 2,3 ADSP-21371KSZ- + Referenced temperature is ambient temperature RoHS Compliant Part 3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www.analog.com/SHARC © ...