adsp-21991 Analog Devices, Inc., adsp-21991 Datasheet

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... PM ADDRESS/DATA DM ADDRESS/DATA SPI SPORT TIMER 0 INTERRUPT WATCHDOG TIMER 1 FLAG CONTROLLER I/O TIMER (ICNTL) TIMER 2 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 Fax:781/326-8703 ADSP-21991 ADDRESS EXTERNAL DATA MEMORY INTERFACE (EMI) CONTROL MEMORY DMA CONTROLLER ADC PIPELINE CONTROL FLASH ADC POR VREF www.analog.com ...

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... Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 36 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 41 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 42 GENERAL DESCRIPTION The ADSP-21991 is a mixed signal DSP controller based on the ADSP-219x DSP Core, suitable for a variety of high performance industrial motor control and signal processing applications that require the combination of a high performance DSP and the mixed signal integration of embedded control peripherals such as analog-to-digital conversion ...

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... REV. 0 The clock generator module of the ADSP-21991 includes clock control logic that allows the user to select and change the main clock frequency. The module generates two output clocks: the DSP core clock, CCLK ...

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... Program memory can store both instructions and data, permit- ting the ADSP-21991 to fetch two operands in a single cycle, one from program memory and one from data memory. The DSP dual memory buses also let the embedded ADSP-219x core fetch an operand from data memory and the next instruction from program memory in a single cycle ...

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... Before a cross page jump or call, the program must set the program sequencer IJPG register to the appropriate memory page. The ADSP-21991 has 4K word of on-chip ROM that holds boot routines. The DSP starts executing instructions from the on-chip boot ROM, which starts the boot process. ...

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... WORDS/PAGE is booting and RESET is active. 2 PERIPHERALS/PAGE The ADSP-21991 asserts the BGH pin when it is ready to start another external port access, but is held off because the bus was previously granted. This mechanism can be extended to define more complex arbitration protocols for implementing more PAGES 32 TO 255 elaborate multimaster systems ...

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... Slave Select outputs (SPISEL1 to SPISEL7) that are multiplexed with the PF1 to PF7 Flag IO lines. The SPISS input is used to select the ADSP-21991 as a slave to an external master. The SPISEL1 to SPISEL7 outputs can be used by the ADSP-21991 (acting as a master) to select/enable up to seven external slaves in an multi device SPI configuration ...

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... At the 20 MHz sampling rate, the first data value is valid approx- imately 375 ns after the Convert Start command. All 8 channels are converted in approximately 725 ns. The core of the ADSP-21991 provides 14-bit data such that the stored data values in the ADC data registers are 14 bits wide. Voltage Reference The ADSP-21991 contains an onboard band gap reference that can be used to provide a precise 1 ...

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... The ADSP-21991 integrates a flexible and programmable, 3- phase PWM waveform generator that can be programmed to generate the required switching patterns to drive a 3-phase voltage source inverter for ac induction (ACIM) or permanent magnet synchronous (PMSM) motor control. In addition, the PWM block contains special functions that considerably simplify ...

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... PWM generation unit of the ADSP-21991. Watchdog Timer The ADSP-21991 integrates a watchdog timer that can be used as a protection mechanism against unintentional software events. It can be used to cause a complete DSP and peripheral reset in such an event. The watchdog timer consists of a 16-bit timer that is clocked at the external clock rate (CLKIN or crystal input frequency) ...

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... Power-Down Core • Power-Down Core/Peripherals • Power-Down All Idle Mode When the ADSP-21991 is in Idle mode, the DSP core stops executing instructions, retains the contents of the instruction pipeline, and waits for an interrupt. The core clock and peripheral clock continue running. ...

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... PLL) resumes executing instructions. Clock Signals The ADSP-21991 can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator crystal oscillator is used, the crystal should be connected across the CLKIN and XTAL pins, with two capacitors ...

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... ROM at address 0xFF0000, irrespective of the settings of the BMODE2, BMODE1, and BMODE0 pins. The dedicated BMODE2, BMODE1, and BMODE0 pins are sampled at hardware reset. The particular boot mode for the ADSP-21991 associated with the settings of the BMODE2, BMODE1, BMODE0 pins is defined in Table 3 ...

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... Analog Devices DSP emulators use the IEEE 1149.1 JTAG Test Access Port of the ADSP-21991 processor to monitor and control the target board processor during emulation. The emulator provides full speed emulation, allowing inspection and modifica- tion of memory, registers, and processor stacks ...

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... ADC Input 7 Inverting SHA_A Input Inverting SHA_B Input Noise Reduction Pin Noise Reduction Pin Voltage Reference Pin (Mode Selected by State of SENSE) Voltage Reference Select Pin Common-Mode Level Pin ADC Convert Start Input General-Purpose IO15 General-Purpose IO14 General-Purpose IO13 –15– ADSP-21991 Table 4: ...

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... ADSP-21991 Table 4. Pin Descriptions (Continued) Pin Type PF12 D, BT, PD PF11 D, BT, PD PF10 D, BT, PD PF9 D, BT, PD PF8 D, BT, PD PF7/SPISEL7 D, BT, PD PF6/SPISEL6 D, BT, PD PF5/SPISEL5 D, BT, PD PF4/SPISEL4 D, BT, PD PF3/SPISEL3 D, BT, PD PF2/SPISEL2 D, BT, PD PF1/SPISEL1 D, BT, PD PF0/SPISS D, BT, PD SCK D, BT MISO D, BT MOSI ...

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... The maximum junction temperature is limited to 140°C in order to meet all of the electrical specifications ultimately the responsibility of the user to ensure that the power dissipation of the ADSP-21991 (including all dc and ac loads) is such that the maximum junction temperature limit of 140°C is not exceeded. ...

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... The I supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK = 150 MHz, DD HCLK = 75 MHz for the ADSP-21991BBC. I consumption at the I/O on the V power supply is very much dependent on the particular connection of the device in the final system. ...

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... The I supply currents are affected by the operating frequency of the device. The guaranteed numbers are based on an assumed CCLK=160 MHz, HCLK MHz for the ADSP-21991BST. I refers only to the current consumption on the internal power supply lines ( the I/O on the V power supply is very much dependent on the particular connection of the device in the final system. ...

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... ADSP-21991 PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21991BBC Parameter ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity ...

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... PERIPHERALS ELECTRICAL CHARACTERISTICS—ADSP-21991BST Parameter ANALOG-TO-DIGITAL CONVERTER AC Specifications SNR Signal-to-Noise Ratio SNRD Signal-to-Noise and Distortion THD Total Harmonic Distortion CTLK Channel-Channel Crosstalk CMRR Common-Mode Rejection Ratio PSRR Power Supply Rejection Ratio Accuracy INL Integral Nonlinearity DNL Differential Nonlinearity ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21991 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... CLKIN and clock multipliers must not select core/peripheral clocks in excess of 160 MHz/80 MHz for the ADSP-21991BST and 150 MHz/75 MHz for the ADSP- 21991BBC, when the peripheral clock rate is one-half the core clock rate. If the peripheral clock rate is equal to the core clock Table 5 ...

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... ADSP-21991 Programmable Flags Cycle Timing Table 6 and Figure 7 describe Programmable Flag operations. Table 6. Programmable Flags Cycle Timing Parameter Timing Requirement t Flag Input Hold is Asynchronous HFI Switching Characteristics t Flag Output Delay with Respect to CLKOUT DFO t Flag Output Hold After CLKOUT High HFO ...

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... Switching Characteristic t Timer Pulsewidth Output HTO 1 The minimum time for t is one cycle, and the maximum time for t HTO HCLK PWM_OUT REV. 0 Min 1 12.5 32 equals (2 –1) cycles. HTO t HTO Figure 8. Timer PWM_OUT Cycle Timing –25– ADSP-21991 Max Unit 32 (2 –1) cycles ns ...

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... ADSP-21991 External Port Write Cycle Timing Table 8 and Figure 9 describe external port write operations. The external port lets systems extend read/write accesses in three ways: wait states, ACK input, and combined wait states and ACK. To add waits with ACK, the DSP must see ACK low at Table 8 ...

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... HCLK t . EMICLK t CSRS ARS t DRSAK t AKW t t CDA t RDA t ADA t SDA Figure 10. External Port Read Cycle Timing –27– ADSP-21991 Min Max t HCLK 3 t –5+W EMICLK EMICLK EMICLK 5 0 0.5t –1 EMICLK 0.5t –3 EMICLK 0.5t –3 EMICLK 0 ...

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... ADSP-21991 External Port Bus Request/Grant Cycle Timing Table 10 and Figure 11 describe external port bus request and bus grant operations. Table 10. External Port Bus Request and Grant Cycle Timing 1, 2 Parameter Timing Requirements BR Asserted to CLKOUT High Setup t BS CLKOUT High to BR Deasserted Hold Time ...

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... RFS Setup Before RCLK and t . DDTLFSE , t and t apply; otherwise, t LSCK DDTLSCK DTENLSCK –29– ADSP-21991 Min Max Unit 1 0.5t –1 ns HCLK 2t ns HCLK ...

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... ADSP-21991 DATA RECEIVE-INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t HOFSE t SFSI RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT-INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSE t HOFSE t SFSI TFS t DDTI t HDTI DT NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE ...

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... BIT t DDTLFSE DRIVE DRIVE SAMPLE t t SFSE/ I HOFSE DDTE / I DTENLFSE t HDTE/ I 1ST BIT t DDTLFSE DRIVE SAMPLE DRIVE t t HOFSE/ I SFSE DDTE/ I DTENLFSE t HDTE/ I 1ST BIT t DDTLFSE –31– ADSP-21991 2ND BIT 2ND BIT ) SCLK 2ND BIT 2ND BIT ) HCLK ...

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... ADSP-21991 Serial Peripheral Interface Port—Master Timing Table 12 and Figure 15 describe SPI port master operations. Table 12. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SCLK Edge (Data Input Setup) SSPID t SCLK Sampling Edge to Data Input Invalid (Data In Hold) ...

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... Figure 16. Serial Peripheral Interface (SPI) Port—Slave Timing REV SPICLS SPICLK t SPICHS DDSPID HDSPID DDSPID MSB t t HSPID SSPID MSB VALID DDSPID MSB t SSPID MSB LSB VALID –33– ADSP-21991 Min Max 2t HCLK 2t HCLK 4t HCLK 2t HCLK 2t +4 HCLK 2t HCLK 1.6 2 HDS ...

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... ADSP-21991 JTAG Test And Emulation Port Timing Table 14 and Figure 17 describe JTAG port operations. Table 14. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK Low ...

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... V. DDINT L are different EXT cannot INT REFERENCE SIGNAL V OH (MEASURED (MEASURED) and the L –35– ADSP-21991 ). The write strobe can switch CK . Select pins switch at 1/( with 50% of the pins switching HCLK = 12.5 ns) HCLK Table 15 EXT 10 ...

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... DECAY on Page 35. Choose ∆ the difference between the output voltage of the ADSP-21991 and the input threshold for the device requiring the hold time. A typical ∆V will be 0 bus capacitance (per data line), and I state current (per data line). The hold time will be t minimum disable time (i ...

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... TRST nc K13 nc K14 TDO MS1 nc L3 GND L4 VDDEXT TMR1 L5 VDDINT CONVST L6 VDDEXT CLKOUT L7 VDDINT –37– ADSP-21991 Ball No. Signal L8 VDDINT L9 VDDEXT L10 VDDEXT L11 GND L12 BMODE2 L13 BMODE1 L14 CLKIN MS2 M3 M4 GND M5 VDDEXT M6 GND ...

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... ADSP-21991 Table 17. 196-Ball Mini-BGA Ball Number by Signal Signal Ball No. Signal A0 N1 CONVST A10 H1 D9 A11 H2 D10 A12 G1 D11 A13 G2 D12 A14 F1 D13 A15 F2 D14 A16 E1 D15 A17 E2 DR ...

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... PF14 nc 127 PF13 PWMSYNC 128 PF12 PWMPOL 129 GND PWMSR 130 nc PWMTRIP 131 nc GND 132 nc –39– ADSP-21991 Lead No. Signal 133 VDDEXT 134 PF11 135 PF10 136 PF9 137 PF8 138 PF7/SPISEL7 139 PF6/SPISEL6 140 PF5/SPISEL5 141 PF4/SPISEL4 142 GND ...

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... ADSP-21991 Table 19. 176-Lead LQFP Lead Number by Signal Signal Lead No. Signal A0 50 CAPB A1 49 CAPT A10 35 CH A11 34 CL A12 33 CLKIN A13 30 CLKOUT A14 29 CML A15 28 CONVST A16 27 D0 A17 26 D1 A18 25 D10 A19 24 D11 A2 48 D12 A3 47 D13 A4 46 D14 A5 40 ...

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... MAX BALL COPLANARITY SEATING PLANE DETAIL A DETAIL B 176-Lead LQFP (ST-176-1) 0.75 0.60 0.45 176 1 PIN 1 1.45 44 1.40 45 1.35 DETAIL A TOP VIEW (PINS DOWN) –41– ADSP-21991 DETAIL 1.00 BSC 13.00 BSC 1.10 1.00 0.90 26.00 BSC SQ 24.00 BSC SQ 133 132 89 88 ...

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... ADSP-21991 Part Number Ambient Temperature Range Instruction Rate Operating Voltage ADSP-21991BBC –40ºC to +85ºC ADSP-21991BST –40ºC to +85ºC ORDERING GUIDE 150 MHz 2.5 Int./3.3 Ext. V 160 MHz 2.5 Int./3.3 Ext. V –42– Package 196-Ball Mini-BGA 176-Lead LQFP REV. 0 ...

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