adsp-21462 Analog Devices, Inc., adsp-21462 Datasheet
adsp-21462
Related parts for adsp-21462
adsp-21462 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Code compatible with all other members of the SHARC family The ADSP-2146x processors are available with unique audio- ...
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... S/PDIF transceiver, and a signal routing unit Digital peripheral interface (DPI) includes, two timers, one UART, and two SPI ports, a DTCP cipher (ADSP-21462W and ADSP-21465W), and a two-wire interface port Outputs of PCG A and B can be routed through DAI pins ...
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... Electrical Characteristics ........................................ 19 Maximum Power Dissipation ................................. 20 Absolute Maximum Ratings ................................... 20 ESD Sensitivity .................................................... 20 Timing Specifications ........................................... 20 Output Drive Currents .......................................... 52 Test Conditions ................................................... 52 Capacitive Loading ............................................... 52 Thermal Characteristics ........................................ 53 Ball configuration - ADSP-21462W/ADSP-21465W/ ADSP-21469W .................................................... 54 PBGA Pinout – ADSP-21462W/ADSP-21465W/ ADSP-21469W ................................................ 55 Ball configuration - ADSP-21467/ADSP-21469 .............. 57 PBGA Pinout - ADSP-21467/ADSP-21469 ................ 58 Outline Dimensions ................................................ 60 Automotive Products ............................................... 61 Ordering Guide ...................................................... 61 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Rev ...
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... Decoder/post-processor algorithm combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information. 2 The ADSP-21462W and ADSP-21465W processors provide the Digital Trans- Yes Yes mission Content Protection protocol, a proprietary security protocol. Contact your Analog Devices sales office for more information. ...
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... Digital peripheral interface that includes two timers, one UART, two serial peripheral interfaces (SPI), a 2-wire interface (TWI), and a flexible signal routing unit (DPI SRU). ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 FAMILY CORE ARCHITECTURE The ADSP-2146x is code compatible at the assembly level with the ADSP-2137x, ADSP-2136x, ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors ...
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... The memory map in address space of the ADSP-21465W and ADSP-21467 proces- sors. The memory map in address space of the ADSP-21462W, ADSP-21469 and ADSP- 21469W processors. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. ...
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... Reserved Reserved 0x0007 4000–0x0007 FFFF 0x000E 8000–0x000F FFFF ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 and data storage. With external execution, programs run at slower speeds since 48-bit instructions are fetched in parts from a 16-bit external bus coupled with the inherent latency of fetch- ing instructions from DDR2 DRAM. VISA mode and SIMD mode accesses are supported for DDR2 space ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 4. ADSP-21462W/ADSP-21469/ADSP-21469W Internal Memory Space IOP Registers 0x0000 0000–0x0003 FFFF Extended Precision Normal or Long Word (64 bits) Instruction Word (48 bits) BLOCK 0 RAM BLOCK 0 RAM 0x0004 9000–0x0004 EFFF 0x0008 C000-0x0009 3FFF Reserved Reserved 0x0004 F000–0x0005 8FFF 0x0009 E000–0x000B 1FFF ...
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... DTCP (or memory-to-mem- ory data transfer when DTCP is not used), two for the link port, two for the FFT/FIR/IIR accelerators, and DMA chan- nels for the media local bus interface on the ADSP-21462W, ADSP-21465W and ADSP-21469W. Programs can be downloaded to the ADSP-2146x using DMA transfers ...
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... DVD content scrambling system) will be protected by this copy protection system. This feature is available on the ADSP-21462W and ADSP-21465W processors only. Licensing through DTLA is required for these products. Visit www.dtcp.com for more information ...
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... Link ports can operate at a maximum frequency of 166 MHz. MediaLB The ADSP-21462W, ADSP-21465W and ADSP-21469W have an MLB interface which allows the processor to function as a media local bus device. It includes support for both 3-pin as well as 5-pin media local bus protocols ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Note that the analog supply pin (V DD_A internal clock generator PLL. To produce a stable clock rec- ommended that PCB designs use an external filter circuit for the V pin. Place the filter components as close as possible to DD_A the V /V pins. For an example circuit, see ...
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... AMI_ACK I (pu AMI_RD O AMI_WR O/T DDR2_ADDR O/T 15–0 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 7: State During SSTL1 and After LVTTL 8 Reset Description High-Z/ External Address. The driven low memory and peripherals on these pins. The data pins can be multi- (boot) plexed to support the PDAP (I) and PWM (O) ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 7. Pin List (Continued) Name Type DDR2_BA O/T 2-0 DDR2_CAS O/T DDR2_CKE O/T DDR2_CS O/T 3-0 DDR2_DATA I/O/T 15-0 DDR2_DM O/T 1-0 DDR2_DQS I/O/T (Differential) 1-0 DDR2_DQS 1-0 DDR2_RAS O/T DDR2_WE O/T DDR2_CLK0, O/T (Differential) DDR2_CLK0, DDR2_CLK1, DDR2_CLK1 DDR2_ODT O/T AMI_MS O/T 0–1 FLAG[0]/IRQ0 I/O FLAG[1]/IRQ1 I/O FLAG[2]/IRQ2/ I/O AMI_MS2 FLAG[3]/TIMEX P/ I/O AMI_MS3 State During SSTL1 and After ...
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... I (pu EMU O/T (pu) CLK_CFG I 1–0 BOOT_CFG I 2–0 RESET I (pu) XTAL O ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 State During SSTL1 and After LVTTL 8 Reset Description High-Z Link Port Data (Link Ports 0–1). When configured as a transmitter, the port drives both the data lines. ...
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... Range of fixed pull-up resistor can be between 26k-63kΩ. Range of fixed pull-down resistor can be between 31k-85kΩ. 3 The MLB pins are only available on the ADSP-21462W/21465W and ADSP-21469W processors. These pins are NC (no connect) on the ADSP-21467 and ADSP-21469 processors. For more information, see PBGA Pinout – ...
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... For details on processor timing, see Timing Specifications Table 10. Core Instruction Rate/ CLKIN Ratio Selection CLKCFG1–0 Core to CLKIN Ratio 00 6:1 01 32:1 11 Reserved 10 16:1 ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 AMI_ADDR [23:8] AMI_ADDR [7:0] AMI_ADDR [23:0] Reserved Reserved FLAGS/PWM [15–0] Reserved PDAP (DATA + CTRL) Reserved Three-state all pins and Figure 3 on Page Rev ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 SPECIFICATIONS OPERATING CONDITIONS 1 Parameter Description V Internal (Core) Supply Voltage DD_INT V External (I/O) Supply Voltage DD_EXT 4 V DDR2 Controller Supply Voltage DD_DDR2 V DDR2 Reference Voltage REF 5 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V ...
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... Applies to three-statable pins with pull-ups: DAI_Px, DPI_Px, EMU. 9 Typical internal current data reflects nominal operating conditions. 10 See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for further information. 11 Applies to all signal pins. 12 Guaranteed, but not tested. ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 450 MHz Test Conditions Min Typical @ V = min 2.4 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 MAXIMUM POWER DISSIPATION See Engineer-to-Engineer Note “Estimating Power Dissipation for ADSP-2146x SHARC Processors” for detailed thermal and power information regarding maximum power dissipation. For information on package thermal specifications, see Characteristics on Page 53. ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed in Table 11 nent damage to the device. These are stress ratings only ...
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... PMCTL DELAY OF RESETOUT RESET 4096 CLKIN CYCLES ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 acteristics describe what the processor will given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing Requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Power-Up Sequencing The timing requirements for processor startup are given in Table 14. Table 14. Power Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V EVDD-DDR2VDD DD_EXT Before V DDR2VDD_IVDD DD_DDR2 1 t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted ...
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... MHz). To achieve the full core clock rate, programs need to configure the multiplier bits in the PMCTL register. In case of the ADSP-21462W, ADSP-21465W, and ADSP-21469W, the maximum clock speed of 400 MHz is arrived at by using a 25 MHz crystal with the default multiplier of 16:1 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Reset Table 16. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST 1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is low, assuming stable V and CLKIN (not including start-up time of external clock oscillator) ...
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... DPI_P14–1 pins through the DPI SRU. Therefore, the timing specifications provided below are valid at the DPI_P14–1 pins. Table 20. Timer PWM_OUT Timing Parameter Switching Characteristic t Timer Pulse Width Output PWMO DPI_P14 - 1 (TIMER1 - 0) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Min TBD t IPW Figure 9. Interrupts Min TBD t WCTIM Figure 10. Core Timer ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Timer WDTH_CAP Timing The following timing specification applies to timer0 and timer1, and in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DPI_P14–1 pins through the SRU. Therefore, the timing specification provided below is valid at the DPI_P14–1 pins. ...
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... DAI_Py DPI_Py PCG_CLKx_O DAI_Pz DPI_Pz PCG_FSx_O ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 inputs and outputs are not directly routed to/from DAI pins (via pin buffers) there is no timing data available. All timing param- eters and switching characteristics apply to external DAI pins (DAI_P01 – DAI_P20). Min TBD ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Flags The timing specifications provided below apply to AMI_ADDR23-0 and AMI_DATA7-0 when configured as FLAGS. See Table 7 on page 13 for more information on flag use. Table 24. Flags Parameter Timing Requirement t DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 IN Pulse Width TBD FIPW Switching Characteristic t DPI_P14-1, AMI_ADDR23-0, AMI_DATA7-0, FLAG3–0 OUT Pulse Width TBD ...
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... Preliminary Technical Data DDR2 SDRAM Read Cycle Timing Table 25. DDR2 SDRAM Read Cycle Timing, V Parameter Symbol Timing Requirements TBD TBD ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 nominal 1.8V DD-DDR2 TBD Figure 16. DDR2 SDRAM Controller Input AC Timing Rev. PrC | Page January 2009 Minimum Maximum Unit TBD TBD ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 DDR2 SDRAM Write Cycle Timing Table 26. DDR2 SDRAM Write Cycle Timing, V Parameter Symbol Switching Characteristics TBD TBD nominal 1.8V DD-DDR2 TBD Figure 17. DDR2 SDRAM Controller Output AC Timing Rev. PrC | Page January 2009 Preliminary Technical Data Minimum Maximum Unit TBD TBD ...
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... Data hold: User must meet t in asynchronous access mode. See HDRH 5 AMI_ACK delay/setup: User must meet DAAK AMI_ADDR MSx t DARL AMI_RD AMI_DATA t DAAK AMI_ACK AMI_WR ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Min 1, 2 TBD 1 TBD TBD 3, 4 TBD 2, 5 TBD 4 TBD TBD TBD 2 TBD TBD TBD ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Memory Write Bus Master — Use these specifications for asynchronous interfacing to memo- ries. Note that timing for AMI_ACK, AMI_DATA, AMI_RD, AMI_WR, and strobe timing parameters only apply to asyn- chronous access mode. Table 28. Memory Write — Bus Master Parameter Timing Requirements ...
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... LACK goes low with tDLALC relative to rise of LCLK after first byte, but does not go low if the receiver's link buffer is not about to fill. LCLK LDAT7-0 LACK (OUT) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 from speed specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew times shown below are calculated to include only one tester guardband ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 30. Link Ports – Transmit Parameter Timing Requirements t LACK Setup Before LCLK High SLACH t LACK Hold After LCLK High HLACH Switching Characteristics t Data Delay After LCLK High DLDCH t Data Hold After LCLK High HLDCH t LCLK Width Low LCLKTWL t LCLK Width High ...
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... SCKLIW 1 Referenced to the sample edge. 2 Referenced to drive edge. ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Serial port signals (SCLK, FS, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Rev. PrC | Page January 2009 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 33. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 34. Serial Ports—External Late Frame Sync ...
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... NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE - DAI_P20 1 SCLK (EXT) t DDTEN - DAI_P20 1 (DATA CHANNEL A/B) DRIVE EDGE - DAI_P20 1 SCLK (INT) t DDTIN DAI_P20 - 1 (DATA CHANNEL A/B) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 SAMPLE EDGE DAI_P20 (SCLK HFSI SFSI DAI_P20 (FS SDRI HDRI DAI_P20 (DATA CHANNEL A/B) SAMPLE EDGE DAI_P20 (SCLK ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Input Data Port (IDP) The timing requirements for the IDP are given in signals (SCLK, FS, and SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications pro- vided below are valid at the DAI_P20–1 pins. Table 35. Input Data Port (IDP) ...
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... AMI_DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins. - DAI_P20 1 (SCLK) - DAI_P20 1 (FS) - DAI_P20 1 (SDATA) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Min TBD TBD TBD TBD TBD TBD SAMPLE EDGE t SRCCLK t SRCCLKW ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Sample Rate Converter—Serial Output Port For the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to SCLK on the output port. The serial data output, SDATA, has a hold time Table 37. ASRC, Serial Output Port ...
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... DAI_P20 (PDAP_CLKEN) DAI_P20 (PDAP_STROBE) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Reference. Note that the most significant 16 bits of external PDAP data can be provided through the DATA7-0 pins. The remaining four bits can only be sourced through DAI_P4–1. The timing below is valid at the DATA7–0 pins. SAMPLE EDGE ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Pulse-Width Modulation Generators (PWM) The following timing specifications apply when the AMI_ADDR23-8 pins are configured as PWM. Table 39. Pulse-Width Modulation (PWM) Timing Parameter Switching Characteristics t PWM Output Pulse Width PWMW t PWM Output Period PWMP PWM OUTPUTS Min TBD TBD t PWMW t PWMP Figure 28 ...
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... DAI_P20-1 LRCLK DAI_P20-1 SCLK MSB MSB-1 MSB-2 DAI_P20-1 SDATA ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 mode) from an LRCLK transition, so that when there are 64 SCLK periods per LRCLK period, the LSB of the data will be right-justified to the next LRCLK transition. LEFT CHANNEL MSB MSB-1 MSB-2 LSB+2 LSB+1 LSB Figure 29 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 S/PDIF Transmitter Input Data Timing The timing requirements for the S/PDIF transmitter are given in Table 40. Input signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. ...
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... Transmit Data Delay After SCLK DDTI t Transmit Data Hold After SCLK HDTI 1 t Transmit SCLK Width SCLKIW 1 SCLK frequency is TBD x FS where FS = the frequency of LRCLK. DAI_P20-1 (DATA CHANNEL A/B) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Min TBD TBD TBD TBD TBD DRIVE EDGE t SCLKIW DAI_P20-1 (SCLK) t DFSI ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 SPI Interface—Master The ADSP-2146x contains two SPI ports. Both primary and sec- ondary are available through DPI only. The timing provided in Table 43 and Table 44 applies to both. Table 43. SPI Interface Protocol—Master Switching and Timing Specifications Parameter Timing Requirements t Data Input Valid To SPICLK Edge (Data Input Setup Time) ...
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... CPHASE = MOSI (INPUT) MISO MSB (OUTPUT CPHASE = 0 MOSI MSB VALID (INPUT) ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 MSB MSB VALID ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing Figure 36 describes UART port receive and transmit operations. The maximum baud rate is PCLK/16 where PCLK = 1/tPCLK. As shown in Figure 36 there is some latency between the gener- Table 45. UART Port Parameter Timing Requirement 1 t Incoming Data Pulse Width ...
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... All values referred to V and V levels. For more information, see Electrical Characteristics on page 19. IHmin ILmax DPI_P14-1 SDA t LOW DPI_P14-1 SCL t HDS DDA T ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Standard Mode Min TBD TBD TBD TBD TBD TBD TBD TBD TBD t SUDA T t HDS TA t SUS TA ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 JTAG Test Access Port and Emulation Table 47. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK High ...
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... Preliminary Technical Data Thermal Diode TBD Media Local Bus TBD ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Rev. PrC | Page January 2009 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 OUTPUT DRIVE CURRENTS Figure 39 shows typical I-V characteristics for the output driv- ers of the ADSP-2146x. The curves represent the current drive capability of the output drivers as a function of output voltage TBD 100 150 0 Figure 39. Typical Drive at Junction Temperature TEST CONDITIONS ...
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... T A Values of θ are provided for package comparison and PCB JC design considerations when an external heatsink is required. ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Values of θ design considerations. Note that the thermal characteristics val- ues provided in Table 48. Thermal Characteristics for 324-Lead PBGA Parameter θ JA θ ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 BALL CONFIGURATION - ADSP-21462W/ADSP-21465W/ADSP-21469W A1 CORNER INDEX AREA Figure 45. ADSP-21462W/ADSP-21465W/ADSP-21469W Ball Configuration – Pin Out DD_INT ...
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... Preliminary Technical Data PBGA PINOUT – ADSP-21462W/ADSP-21465W/ADSP-21469W Table 49 PBGA Pin Assignment (Alphabetically by Signal) Signal Ball AMI_ACK R10 AMI_ADDR0 V16 AMI_ADDR01 U16 AMI_ADDR02 T16 AMI_ADDR03 R16 AMI_ADDR04 V15 AMI_ADDR05 U15 AMI_ADDR06 T15 AMI_ADDR07 R15 AMI_ADDR08 V14 AMI_ADDR09 U14 AMI_ADDR10 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Table 49 PBGA Pin Assignment (Alphabetically by Signal) (Continued) Signal Ball V D18 DDR V E02 DDR V E04 DDR V E07 DDR V E10 DDR V E11 DDR V E17 DDR V F03 DDR V F05 DDR V F15 ...
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... Preliminary Technical Data BALL CONFIGURATION - ADSP-21467/ADSP-21469 A1 CORNER INDEX AREA ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 DD_INT DD_DDR2 V REF V R DD_EXT ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 PBGA PINOUT - ADSP-21467/ADSP-21469 Table 50 PBGA Pin Assignment (Alphabetically by Signal) Signal Ball AMI_ACK R10 AMI_ADDR0 V16 AMI_ADDR01 U16 AMI_ADDR02 T16 AMI_ADDR03 R16 AMI_ADDR04 V15 AMI_ADDR05 U15 AMI_ADDR06 T15 AMI_ADDR07 R15 AMI_ADDR08 V14 AMI_ADDR09 U14 AMI_ADDR10 T14 AMI_ADDR11 R14 ...
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... DD INT V E09 _ DD INT V E14 _ DD INT V E15 _ DD INT V F06 _ DD INT V F07 _ DD INT V F08 _ DD INT ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 Signal Ball Signal V F09 INT SS V F10 INT SS V F11 INT SS V F12 INT SS V F13 ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 OUTLINE DIMENSIONS The ADSP-2146x processors are available PBGA lead-free package. BALL A1 PAD CORNER 2.40 2.28 2.16 19.20 19.00 SQ 18.80 17.00 17.05 BSC SQ 16.95 SQ 16.85 1.00 BSC TOP VIEW 1.00 REF DETAIL A 0.61 NOM 0.50 NOM 0.40 MIN SEATING PLANE COMPLIANT TO JEDEC STANDARDS MS-034-BAR-2 Figure 47. 324-Ball Plastic Ball Grid Array [PBGA] (B-324) Dimensions shown in millimeters Rev ...
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... Preliminary Technical Data AUTOMOTIVE PRODUCTS The ADSP-21462W, ADSP-21465W, and ADSP-21469W are available for automotive applications with controlled manufac- turing. Note that these special models may have specifications that differ from the general release models. Table 51. Automotive Products 1 Model Temperature Range –40°C to +85°C AD21462WBBZ3xx – ...
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... ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469 ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07809-0-1/09(PrC) Rev. PrC | Page January 2009 Preliminary Technical Data ...