adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet
adsp-21266skstz-2b
Available stocks
Related parts for adsp-21266skstz-2b
adsp-21266skstz-2b Summary of contents
Page 1
... On-chip memory— bits on-chip SRAM and a dedi cated 4M bits on-chip mask-programmable ROM The ADSP-2126x processors are available with a 150 MHz or a 200 MHz core instruction rate. For complete ordering information, see ...
Page 2
... TDM streams 128 channels per frame At 200 MHz (5 ns) core instruction rate, the ADSP-2126x oper ates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed- or floating-point data; 400 MMACS sustained performance at 200 MHz Super Harvard Architecture— ...
Page 3
... Outline Dimensions ................................................ 45 Surface-Mount Design .......................................... 45 Ordering Guide ...................................................... 47 ADSP-21261/ADSP-21262/ADSP-21266 REVISION HISTORY 7/08—Rev Rev. E This revision of the data sheet combines the ADSP-21261 and ADSP-21262 into the ADSP-21266 data sheet. Corrected all outstanding document errata. Corrected block diagram............................................. Added Extended Precision Normal or Instruction Word (48 Bits) to ...
Page 4
... Assumes two files in multichannel SIMD mode. As shown in the functional block diagram in the ADSP-2126x uses two computational units to deliver times performance increase over previous SHARC proces sors on a range of DSP algorithms. Fabricated in a state-of-the art, high speed, CMOS process, the ADSP-2126x DSPs achieve an instruction cycle time 200 MHz or 6 ...
Page 5
... The registers in PEX are referred to as R0–R15 and in PEY as S0–S15. Single-Cycle Fetch of Instruction and Four Operands The ADSP-2126x features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the pro gram memory (PM) bus transfers both instructions and data ...
Page 6
... MPEG2 BC 2ch Noise DPL2x/EX Neo:6/ES (v2.5046) The ADSP-2126x’s SRAM can be configured as a maximum of 64K words of 32-bit data, 128K words of 16-bit data, 42K words of 48-bit instructions (or 40-bit data), or combinations of differ ent word sizes up to two megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float ...
Page 7
... ADSP-2126x’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) port, the IDP (input data port), parallel data acquisition port (PDAP), or the parallel port channels of DMA are available on the ADSP-2126x—one for the SPI interface, 12 via ADSP-21261/ADSP-21262/ADSP-21266 Normal Word (32 Bits) Block 0 SRAM 0x0008 0000– ...
Page 8
... Timers The ADSP-2126x has a total of four timers: a core timer able to generate periodic software interrupts, and three general-pur pose timers that can generate periodic interrupts and be independently set to operate in one of three modes: • ...
Page 9
... VSS the chip. TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-2126x pro cessor to monitor and control the target board processor during ADSP-21261/ADSP-21262/ADSP-21266 V DDINT emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces ...
Page 10
... ADSP-21261/ADSP-21262/ADSP-21266 The VisualDSP++ debugger has a number of important fea tures. Data visualization is enhanced by a plotting package that offers a significant level of flexibility. This graphical representa tion of user data enables the programmer to quickly determine the performance of an algorithm. As algorithms grow in com ...
Page 11
... This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-2126x architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x SHARC DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference ...
Page 12
... ADSP-21261/ADSP-21262/ADSP-21266 PIN FUNCTION DESCRIPTIONS The ADSP-2126x pin definitions are listed below. Inputs identi fied as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchro nously to CLKIN (or to TCK for TRST). Tie or pull unused ...
Page 13
... If SPI master boot mode is selected, MOSI and SPICLK pins are driven during reset. These pins are not three-stated during reset in SPI master boot mode. SPI Master In Slave Out. If the ADSP-2126x is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-2126x is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data ...
Page 14
... Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-2126x. TRST has a 22.5 kΩ internal pull-up resistor. Emulation Status. Must be connected to the ADSP-2126x Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 22.5 kΩ ...
Page 15
... Reserved ADSP-21261/ADSP-21262/ADSP-21266 ADDRESS DATA MODES Table 10 shows the functionality of the AD pins for 8-bit and 16-bit transfers to the parallel port. For 8-bit data transfers, ALE latches address bits A23–A8 when asserted, followed by address bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit data transfers, ALE latches address bits A15– ...
Page 16
... ADSP-21261/ADSP-21262/ADSP-21266 PRODUCT SPECIFICATIONS OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage _ IH CLKIN V Low Level Input Voltage @ ...
Page 17
... Storage Temperature Range Junction Temperature Under Bias TIMING SPECIFICATIONS The ADSP-2126x’s internal clock (a multiple of CLKIN) pro vides the clock signal for timing internal memory, processor core, serial ports, and parallel port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP’ ...
Page 18
... The shaded divider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (PMCTL). For more information, see the ADSP-2126x SHARC Processor Peripherals Reference and Managing the Core PLL on Third- Generation SHARC Processors (EE-290). ...
Page 19
... The 4096 cycle count depends on t specification in SRST 4097 cycles maximum. RESET V DDINT V DDEXT CLKIN CLK_CFG1–0 RESETOUT (MULTIPLEXED WITH CLKOUT) ADSP-21261/ADSP-21262/ADSP-21266 Table DDINT DDEXT DDEXT 1 /V Valid DDINT DDEXT Table 17. If setup time is not met, one additional CLKIN cycle can be added to the core reset time, resulting in ...
Page 20
... CKH Figure 7. Clock Input Clock Signals The ADSP-2126x can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-2126x to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun ...
Page 21
... FLAG0, FLAG1, and FLAG2 pins when they are configured as IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins when configured as interrupts. Table 18. Interrupts Parameter Timing Requirements t IRQx Pulse Width IPW ADSP-21261/ADSP-21262/ADSP-21266 Min 4 × WRST Figure 9. Reset Figure 10 applies to the DAI_P20– ...
Page 22
... ADSP-21261/ADSP-21262/ADSP-21266 Core Timer The timing specification in Table 19 and FLAG3 when it is configured as the core timer (CTIMER). Table 19. Core Timer Parameter Switching Characteristics t CTIMER Pulse Width WCTIM TIM Timer PWM_OUT Cycle Timing The timing specification in Table 20 and Timer in PWM_OUT (pulse-width modulation) mode. Timer signals are routed to the DAI_P20– ...
Page 23
... SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 21. Timer Width Capture Timing Parameter Timing Requirements t Timer Pulse Width PWI DAI_P20–1 (TIMER) ADSP-21261/ADSP-21262/ADSP-21266 Figure 13 applies to Min 2 × t CCLK t PWI Figure 13. Timer Width Capture Timing Rev Page July 2008 ...
Page 24
... ADSP-21261/ADSP-21262/ADSP-21266 DAI Pin-to-Pin Direct Routing See Table 22 and Figure 14 for direct pin connections only (for example, DAI_PB01_I to DAI_PB02_O). Table 22. DAI Pin-to-Pin Routing Parameter Timing Requirements t Delay DAI Pin Input Valid to DAI Output Valid DPIO DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin-to-Pin Direct Routing Rev ...
Page 25
... DAI_Py PCG_CLKx_O DAI_Pz PCG_FSx_O ADSP-21261/ADSP-21262/ADSP-21266 cases where the PCG’s inputs and outputs are not directly routed to/from DAI pins (via pin buffers), there is no timing data available. All timing parameters and switching characteris tics apply to external DAI pins (DAI_P07–DAI_P20). ...
Page 26
... ADSP-21261/ADSP-21262/ADSP-21266 Flags The timing specifications in Table 24 and FLAG3–0 and DAI_P20–1 pins, the parallel port, and the serial peripheral interface. See Table 6 on Page 12 tion on flag use. Table 24. Flags Parameter Timing Requirements t FLAG3–0 IN Pulse Width FIPW Switching Characteristics t FLAG3–0 OUT Pulse Width FOPW DAI_P20– ...
Page 27
... Memory Read—Parallel Port The specifications in Table 25, Table 26, Figure 18 are for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2126x is access ing external memory space. Table 25. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
Page 28
... ADSP-21261/ADSP-21262/ADSP-21266 Table 26. 16-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 15–0 Setup Before RD high DRS t Address/Data 15–0 Hold After RD high DRH Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS t 1 Address/Data 15–0 Hold After ALE Deaserted ...
Page 29
... Memory Write—Parallel Port Use the specifications in Table 27, Table Figure 20 for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-2126x is access ing external memory space. Table 27. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ...
Page 30
... ADSP-21261/ADSP-21262/ADSP-21266 Table 28. 16-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS 1 t Address/Data 15–0 Hold After ALE Deasserted ADAH t WR Pulse Width ALE Deasserted to Address/Data 15–0 in High-Z ...
Page 31
... Transmit or Receive SCLK Width SCLKIW 1 Referenced to the sample edge. 2 Referenced to drive edge. ADSP-21261/ADSP-21262/ADSP-21266 Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Table 29, ...
Page 32
... ADSP-21261/ADSP-21262/ADSP-21266 Table 31. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 32. Serial Ports—External Late Frame Sync ...
Page 33
... NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE. DRIVE EDGE DAI_P20–1 SCLK (EXT) DAI_P20–1 (DATA CHANNEL A/B) DRIVE EDGE DAI_P20–1 SCLK (INT) DAI_P20–1 (DATA CHANNEL A/B) ADSP-21261/ADSP-21262/ADSP-21266 SAMPLE EDGE DAI_P20–1 (SCLK HFSI SFSI DAI_P20–1 (FS) t ...
Page 34
... ADSP-21261/ADSP-21262/ADSP-21266 Input Data Port (IDP) The timing requirements for the IDP are given in Figure 23. IDP Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica tions provided below are valid at the DAI_P20–1 pins. ...
Page 35
... The timing requirements for the PDAP are provided in and Figure 24. PDAP is the parallel mode operation of Channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2126x Peripherals Manual. Table 34. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements t ...
Page 36
... ADSP-21261/ADSP-21262/ADSP-21266 SPI Interface Protocol—Master Table 35. SPI Interface Protocol—Master Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Setup Time) SSPIDM t SPICLK Last Sampling Edge to Data Input Not Valid HSPIDM Switching Characteristics t Serial Clock Cycle SPICLKM t Serial Clock High Period ...
Page 37
... MOSI MSB VALID (INPUT MISO MSB (OUTPUT) CPHASE = 0 MOSI MSB VALID (INPUT) ADSP-21261/ADSP-21262/ADSP-21266 MSB LSB VALID t t ...
Page 38
... ADSP-21261/ADSP-21262/ADSP-21266 JTAG Test Access Port and Emulation Table 37. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High SSYS ...
Page 39
... OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output driv ers of the ADSP-2126x. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125°C 0 –10 3.11V, 125°C –20 – 3.47V, – ...
Page 40
... LOAD CAPACITANCE (pF) Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-2126x processor is rated for performance under T environmental conditions specified in the tions on Page 16. THERMAL CHARACTERISTICS Table 38 and Table 39 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to ...
Page 41
... LQFP PIN CONFIGURATIONS Table 40 shows the ADSP-2126x’s pin names and their default function after reset (in parentheses). Table 40. 144-Lead LQFP Pin Assignments LQFP Pin Name Pin No. Pin Name DDINT DDINT CLK_CFG0 2 GND CLK_CFG1 3 RD BOOT_CFG0 4 ALE BOOT_CFG1 5 AD15 GND ...
Page 42
... ADSP-21261/ADSP-21262/ADSP-21266 136-BALL BGA PIN CONFIGURATIONS Table 41 shows the ADSP-2126x’s pin names and their default function after reset (in parentheses). Figure 34 on Page 44 shows the BGA package pin assignments. Table 41. 136-Ball BGA Pin Assignments BGA Pin Pin Name No. Pin Name CLK_CFG0 A01 ...
Page 43
... DAI_P4 (SFS0) N10 DAI_P6 (SD1B) V N11 DAI_P7 (SCLK1) DDINT V N12 DAI_P8 (SFS1) DDINT GND N13 DAI_P9 (SD2A) DAI_P10 (SD2B) N14 DAI_P11 (SD3A) ADSP-21261/ADSP-21262/ADSP-21266 BGA Pin No. Pin Name K01 AD2 K02 AD1 K04 GND K05 GND K06 GND K09 GND K10 GND ...
Page 44
... ADSP-21261/ADSP-21262/ADSP-21266 Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary KEY V A GND DDINT VDD V A I/O SIGNALS DDEXT VSS * USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Rev Page July 2008 ...
Page 45
... OUTLINE DIMENSIONS The ADSP-2126x is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 36 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ADSP-21261/ADSP-21262/ADSP-21266 and Figure 35. 0.75 1.60 0.60 MAX 0.45 144 1 PIN 1 0.20 0.09 7° 3.5° 0° 36 0.08 37 COPLANARITY VIEW A COMPLIANT TO JEDEC STANDARDS MS-026-BFB Figure 35. 144-Lead Low Profile Flat Package [LQFP] ...
Page 46
... ADSP-21261/ADSP-21262/ADSP-21266 1.70 MAX SURFACE-MOUNT DESIGN Table 42 is provided as an aide to PCB design. For industry- standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard. Table 42. BGA_ED Data for Use with Surface-Mount Design Package Ball Attach Type 136-Ball CSP_BGA (BC-136) Solder Mask Defined (SMD) 12 ...
Page 47
... ADSP-21262SKBC-200 0°C to +70°C 2 ADSP-21262SKBCZ200 0°C to +70°C 2 ADSP-21262SKSTZ200 0°C to +70° ADSP-21266SKSTZ-1B 0°C to +70° ADSP-21266SKSTZ-2B 0°C to +70° ADSP-21266SKBCZ-2B 0°C to +70° ADSP-21266SKSTZ-1C 0°C to +70° ADSP-21266SKSTZ-2C 0°C to +70° ADSP-21266SKBCZ-2C 0° ...
Page 48
... ADSP-21261/ADSP-21262/ADSP-21266 ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04932-0-7/08(E) Rev Page July 2008 ...