adsp-21mod870-100 Analog Devices, Inc., adsp-21mod870-100 Datasheet

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adsp-21mod870-100

Manufacturer Part Number
adsp-21mod870-100
Description
Internet Gateway Processor
Manufacturer
Analog Devices, Inc.
Datasheet
a
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
PERFORMANCE
Complete Single-Chip Internet Gateway Processor (No
Implements V.34/V.90 Data/FAX Modem Including
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS Sustained
Open Architecture Platform Extensible to Voice Over IP
Low Power Dissipation, 80 mW (Typical) for Digital
Power-Down Mode Featuring Low CMOS Standby
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
160K Bytes of On-Chip RAM, Configured as 32K Words
Dual Purpose Program Memory for Both Instruction
Independent ALU, Multiplier/Accumulator and Barrel
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP with 0.4 Square Inch (256 mm
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to On-
Two Double-Buffered Serial Ports with Companding
Programmable Multichannel Serial Port Supports
Automatic Booting of On-Chip Program Memory
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
ICE-Port™ Emulator Interface Supports Debugging in
External Memory Required)
Controller and Datapump
Performance
and Other Applications
Modem
Power Dissipation
Set Extensions
On-Chip Program Memory RAM and 32K Words On-
Chip Data Memory RAM
and Data Storage
Shifter Computational Units
Looping Conditional Instruction Execution
Chip Memory (Mode Selectable)
Hardware and Automatic Data Buffering
24/32 Channels
Through Internal DMA Port
Signaling
Final Systems
2
) Footprint
GENERAL DESCRIPTION
The ADSP-21mod870 is a single-chip Internet gateway pro-
cessor optimized for implementation of a complete V.34/56K
modem. All data pump and controller functions can be imple-
mented on a single chip, offering the lowest power consumption
and highest possible modem port density.
The ADSP-21mod870, shown in the Functional Block Dia-
gram, combines the ADSP-2100 family base architecture (three
computational units, data address generators and a program
sequencer) with two serial ports, a 16-bit internal DMA port, a
byte DMA port, a programmable timer, Flag I/O, extensive
interrupt capabilities and on-chip program and data memory.
The ADSP-21mod870 integrates 160K bytes of on-chip
memory configured as 32K words (24-bit) of program RAM,
and 32K words (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery operated
portable equipment. The ADSP-21mod870 is available in
100-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-21mod870 operates with a 19 ns instruction cycle time.
Every instruction can execute in a single processor cycle.
The ADSP-21mod870’s flexible architecture and comprehen-
sive instruction set allow the processor to perform multiple
operations in parallel. In one processor cycle the ADSP-21mod870
can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
DATA ADDRESS
GENERATORS
DAG 1
ALU
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG 2
Internet Gateway Processor
MAC
SEQUENCER
SHIFTER
PROGRAM
FUNCTIONAL BLOCK DIAGRAM
PROGRAM MEMORY DATA
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
DATA MEMORY DATA
World Wide Web Site: http://www.analog.com
16K 24 PM
8K 24 OVERLAY 1
8K 24 OVERLAY 2
SPORT 0
ADSP-21mod870
SERIAL PORTS
POWER-DOWN
CONTROL
MEMORY
SPORT 1
16K 16 DM
8K 16 OVERLAY 1
8K 16 OVERLAY 2
© Analog Devices, Inc., 1999
TIMER
PROGRAMMABLE
FLAGS
AND
I/O
FULL MEMORY
HOST MODE
CONTROLLER
EXTERNAL
EXTERNAL
EXTERNAL
INTERNAL
ADDRESS
BYTE DMA
DATA
PORT
DATA
DMA
BUS
BUS
BUS
MODE
OR

Related parts for adsp-21mod870-100

adsp-21mod870-100 Summary of contents

Page 1

... The ADSP-21mod870 is available in 100-lead LQFP package. Fabricated in a high speed, low power, CMOS process, the ADSP-21mod870 operates with instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-21mod870’s flexible architecture and comprehen- sive instruction set allow the processor to perform multiple operations in parallel ...

Page 2

... EZ-ICE target board connector. ADSP-21mod870 Reference Design/Evaluation Kit The ADSP-21mod870-EV1 is a reference design/evaluation kit that includes an ISA bus PC card that has an ADSP-21061L ® SHARC processor as a host, four ADSP-21mod870 Internet gateway processors and a T1 interface. The board is shipped with an evaluation copy of the modem software and software that runs on the PC ...

Page 3

... ADSP-2100 Family Development Tools data sheet. For more information about the modem software refer to ADSP-21mod870-100 Modem Software data sheet. ARCHITECTURE OVERVIEW The ADSP-21mod870 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions ...

Page 4

... The ADSP-21mod870 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-21mod870 SPORTs. For additional information on Serial Ports, refer to the ADSP-2100 Family User’s Manual, Third Edition. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • ...

Page 5

... Memory Interface Pins The ADSP-21mod870 processor can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running ...

Page 6

... Here is a brief list of power-down features. Refer to the ADSP-2100 Fam- ily User’s Manual, Third Edition, “System Interface” chapter, for detailed information about the power-down feature. ...

Page 7

... ADSP-21mod870. The ADSP- 21mod870 can support channels. The IDMA port of the ADSP-21mod870 is used to give a host processor full access to the internal memory of the ADSP-21mod870. This lets the host dynamically configure the ADSP-21mod870 by loading code and data into its internal memory. This configuration also lets the host access server data directly from the ADSP-21mod870’ ...

Page 8

... MODES OF OPERATION Table II summarizes the ADSP-21mod870 memory modes. Setting Memory Mode The ADSP-21mod870 uses the Mode C pin to make a Memory Mode selection during chip reset. This pin is multiplexed with the processor’s PF2 pin, so exercise care when selecting a mode. The two methods for selecting the value of Mode C are active and passive ...

Page 9

... MEMORY ARCHITECTURE The ADSP-21mod870 provides a variety of memory and pe- ripheral interface options. The key functional groups are Pro- gram Memory, Data Memory, Byte Memory and I/O. Refer to the following figures and tables for PM and DM memory alloca- tions in the ADSP-21mod870 ...

Page 10

... BDMA feature. The byte memory space consists of 256 pages, each of which is 16K 8. The byte memory space on the ADSP-21mod870 supports read and write operations as well as four different data formats. The byte memory uses data bits 15:8 for data. The byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address ...

Page 11

... Internal Memory DMA Port (IDMA Port; Host Memory Mode) The IDMA Port provides an efficient means of communication between a host system and the ADSP-21mod870. The port is used to access the on-chip program memory and data memory of the processor with only one processor cycle per word over- head ...

Page 12

... DMS, BMS, CMS, IOMS, RD, WR output drivers, OVLAY • Asserting the bus grant (BG) signal and ALWAYS • Halting program execution Mode is enabled, the ADSP-21mod870 will not halt pro- 0x0000– 0x1FFF gram execution until it encounters an instruction that requires an 0x0000– ...

Page 13

... The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when the ADSP-21mod870 is ready to execute an instruction but is stopped because the external bus is already granted to another device. The other device can release the bus by deasserting bus request ...

Page 14

... Restriction: All memory strobe signals on the ADSP-21mod870 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 k pull-up resistors connected when the EZ-ICE is being used ...

Page 15

... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7 BR. 9 Idle refers to ADSP-21mod870 state of operation during execution of IDLE instruction. Deasserted pins are driven to either and 3 V. For typical figures for supply currents, refer to Power Dissipation section. ...

Page 16

... Permanent damage may occur to devices subjected to high energy electrostatic discharges. The ADSP-21mod870 features proprietary ESD protection circuitry to dissipate high energy discharges (Human Body Model) per method 3015 of MIL-STD-883. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

Page 17

... V f) POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS IDLE REFERS TO ADSP-21mod870 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V 3 TYPICAL POWER DISSIPATION AT 3. MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL DD MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS ...

Page 18

... ADSP-21mod870 CAPACITIVE LOADING Figures 16 and 17 show the capacitive loading characteristics of the ADSP-21mod870 + 30V 100 150 C – Figure 16. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature ...

Page 19

... CKI t CKIL t CKOH t CKH t CKL RSP * , PF3 IS MODE D PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A Figure 21. Clock Signals –19– ADSP-21mod870 Max 100 – – CKIH Unit ...

Page 20

... IFS IFH following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User’s Manual, Third Edition, for further information on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns ...

Page 21

... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...

Page 22

... ADSP-21mod870 TIMING PARAMETERS Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, xMS Setup before RD Low t ASR A0–A13, xMS Hold after RD Deasserted ...

Page 23

... CK 0 0.25 t – 0.25 t – 0.25 t – 0.75 t – 0.25 t – 0.5 t – WRA ASW CWR WDE Figure 25. Memory Write –23– ADSP-21mod870 Max Unit 0. WWR t DDR ...

Page 24

... ADSP-21mod870 TIMING PARAMETERS Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid ...

Page 25

... Start of Write or Read = IS Low and IWR Low or IRD Low. IACK IAL IS IAD15–0 IRD OR IWR REV IKA t IALD t t IALP IALP t t IASU IASU t IAH Figure 27. IDMA Address Latch –25– ADSP-21mod870 Min Max IAH t IALS Unit ...

Page 26

... ADSP-21mod870 TIMING PARAMETERS Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristics: Start of Write to IACK High ...

Page 27

... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition. IACK IS IWR IAD15– ...

Page 28

... ADSP-21mod870 Parameter IDMA Read, Short Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Hold after End of Read IKDH t IAD15–0 Data Disabled after End of Read ...

Page 29

... IKHR t IKR IKDS IRDE PREVIOUS READ DATA DATA t IRDV t IRDH Figure 31. IDMA Read, Long Read Cycle –29– ADSP-21mod870 Min Max 0.5 t – – – IRK t IKDH t IKDD Unit ...

Page 30

... XTAL CLKOUT 16 GND BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 100-Lead LQFP Package Pinout PIN 1 IDENTIFIER ADSP-21mod870 TOP VIEW (Not to Scale) –30– D15 75 D14 74 73 D13 72 D12 71 GND D11 70 D10 GND D7/IWR ...

Page 31

... The ADSP-21mod870 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when Mode sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ּ ] are state bits latched from the value of the pin at the deassertion of RESET. ...

Page 32

... ADSP-21mod870 100-Lead Metric Thin Plastic Quad Flatpack (LQFP) Ambient Temperature Part Number Range ADSP-21mod870-000 +70 C OUTLINE DIMENSIONS Dimensions shown in inches and (mm). (ST-100) 0.640 (16.25) 0.630 (16.00) 0.620 (15.75) 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) 0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) TYP 100 12° 0.020 (0.50) 1 TYP SEATING PLANE TOP VIEW (PINS DOWN) 0 ...

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