saa7110 NXP Semiconductors, saa7110 Datasheet
saa7110
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saa7110 Summary of contents
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... DATA SHEET SAA7110; SAA7110A One Chip Front-end 1 (OCF1) Product specification File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 1995 Oct 18 ...
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... I C-BUS START SET-UP 21.1 Remarks to Table 66 22 APPLICATION INFORMATION 23 START-UP, SOURCE SELECT AND STANDARD DETECTION FLOW EXAMPLE 1995 Oct 18 SAA7110; SAA7110A 23.1 CODE 0 STARTUP and STANDARD Procedure 23.2 MODE 0 Source Select Procedure 23.3 MODE 1 Source Select Procedure 23.4 MODE 2 Source Select Procedure 23.5 MODE 3 Source Select Procedure 23 ...
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... Video phone Video picture grabbing. 3 GENERAL DESCRIPTION The one chip front-end SAA7110; SAA7110A is a digital multistandard colour decoder (OCF1) on the basis of the DIG-TV2 system with two integrated Analog-to-Digital Converters (ADCs), a Clock Generation Circuit (CGC) and Brightness Contrast Saturation (BCS) control. ...
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... PACKAGE DESCRIPTION plastic leaded chip carrier; 68 leads plastic leaded chip carrier; 68 leads PC ISA - BUS ONE VIDEO CHIP MEMORY FRONT-END CONTROLLER OCF1 VMC clock YUV - BUS Fig.1 System diagram. 4 Product specification SAA7110; SAA7110A VERSION SOT188-2 SOT188-2 VIDEO FRAME MEMORY MGC821 ...
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... AP TEST CONTROL BLOCK 1 SP 68, 52, 44, 67, 51, 43, 35 BYPASS CHROMINANCE C/CVBS CIRCUIT LUMINANCE CIRCUIT UV Y/CVBS Y Y SYNCHRONIZATION SAA7110 CIRCUIT SAA7110A PLIN (HL HSY HCL RTCO ODD (VL) Fig.2 Block diagram C-BUS 5 SDA INTERFACE 6 SCL ...
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... Using CREF all interfaces on the YUV-bus are able to generate a bus timing with identical phase. 1995 Oct 18 DESCRIPTION f for 50 Hz/625 lines per field systems and 1560 h 1 output 0.5 f (CGCE = 1, output; CGCE = 0, high 2 LLC2 LLC 6 Product specification SAA7110; SAA7110A f for h ...
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... C-bus register 05H mode or register 18H mode. 2 C-bus bit RTSE = 1). 2 C-bus bit RTSE = 0. 2 C-bus bit RTSE = 1). 7 Product specification SAA7110; SAA7110A 2 C-bus is reset (waiting for 2 C-bus bit PULIO: PULIO = 1, 2 C-bus bit PULIO: 2 C-bus 2 C-bus bit RTSE = 0. ...
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... C-bus control. These signals are part of the digital YUV-bus 2 C-bus bits MS24 and MS34 and MUYC to LOW. 2 C-bus bit VBLKA = 0. (Vertical Blank test output; select 2 C-bus bit VBLKA = 1). 8 Product specification SAA7110; SAA7110A 2 C-bus bit SQPB = 1. 2 C-bus bit SQPB = 1. 2 C-bus bit SQPB = 1. 2 C-bus register ...
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... AI31 18 V SSA2 AI22 DDA2 21 AI21 V 22 SS(S) AOUT 23 V DDA0 24 V SSA0 25 26 LFCO 1995 Oct 18 SAA7110 SAA7110A Fig.3 Pin configuration. 9 Product specification SAA7110; SAA7110A 60 UV2 59 UV3 58 UV4 57 UV5 56 UV6 55 UV7 ...
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... FUNCTIONAL DESCRIPTION 9.1 Analog input processing (see Fig.5) The SAA7110; SAA7110A offers six analog signal inputs, two analog main channels with clamping circuit, analog amplifier, anti-alias filter and video CMOS ADC. A third analog channel also with clamping circuit, analog amplifier and anti-alias filter can be added or switched to both main channels directly before the ADCs ...
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... The pre-filtered luminance signal is fed to the synchronization stage. It's bandwidth is reduced to 1 MHz in a low-pass filter. 1995 Oct 18 SAA7110; SAA7110A The synchronization pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations ...
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Acrobat reader. white to force landscape pages to be ... 20, 16 DDA2 to V DDA4 18, 14 SSA2 to ...
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Acrobat reader. white to force landscape pages to be ... INPUT CHROMINANCE QUADRATURE INTERFACE BANDPASS DEMODULATOR BYPS DISCRETE TIME CHRS OSCILLATOR HUEC (DTO1) AND ...
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Acrobat reader. white to force landscape pages to be ... LUMINANCE CIRCUIT CHROMINANCE PREFILTER TRAP PREF BYPS 2 AP TEST CONTROL 1 SP BLOCK ...
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... HSY = horizontal sync pulse. HCL = horizontal clamp pulse. 1995 Oct 18 ANALOG IN ADC 1 0 VBLK CLAMP 0 HCL CLAA 0 1 SBOT 0 NO CLAMP GAIN Fig.8 Clamp and gain flow chart. 15 Product specification SAA7110; SAA7110A GAIN 1 0 HSY WIPE GAIN GAIN SLOW GAIN MGC827 ...
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... WIRS 4/F 4/L IVAL IVAL *IWIP *IGAI gain accumulator (20 bits) actual gain value 8-bit (AGV dB AGV Fig.9 Luminance AGC flow chart. 16 Product specification SAA7110; SAA7110A decoder input 1 0 HSY WIPE X 1 WVAL / 0 *IWIP 0 0 HSY ...
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... note 1 DDA DDD note 2 CONDITIONS couple clamping current off f < 5 MHz amplifier + AAF = bypass amplifier + AAF = bypass 17 Product specification SAA7110; SAA7110A MIN. MAX. 0.5 +7.0 0.5 +7.0 0.5 +7.0 0.5 +7.0 100 65 +150 +80 2.5 2000 +2000 MIN. TYP. ...
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... FEIN HD;FEIN t input data hold time all other HD;OTHER inputs 1995 Oct 18 CONDITIONS I/Os at high impedance note 1 note 2 note 0 2 note 3 18 Product specification SAA7110; SAA7110A MIN. TYP. MAX. 0.5 +1.5 3 0.5 DD 0.5 +0.6 2 0 0.5 DD 0.5 +0.8 2 ...
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... LLC 0.6 to 2.6 V 2 pF; note 6 LLC/LLC2 field 60 Hz field 50 Hz field 60 Hz field PAL NTSC 19 Product specification SAA7110; SAA7110A MIN. TYP. MAX 7 31 15625 15734 5 ...
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... Oct 18 CONDITIONS MIN. 3rd harmonic pF: data outputs (plus HREF and VS); 1 (TTL load); L TYPICAL ANALOG DELAY AI21 TO ADCIN (AOUT) (ns Product specification SAA7110; SAA7110A TYP. MAX. UNIT 26.8 MHz + + ...
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... CLOCK OUTPUT LLC2 1995 Oct LLCH HD;DAT t SU;DAT t OHD PDZ t OHD LLCL LLCH OHD t dLLC2 Fig.10 Clock/data timing. 21 Product specification SAA7110; SAA7110A 2.4 V 1 2 HD;DAT 2 HD;DAT 2.4 V 0.6 V 2.6 V 1 OHD 2.4 V 0 ...
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... HRMV = 1 and HRFS = 0. 1995 Oct 2/LLC burst 191 127 processing delay CVBS 18 768 2/LLC 94 2/LLC 30 2/LLC 64 2/LLC 117 0 18 140 640 2/LLC 64 2/LLC 97 0 Fig.11 Horizontal timing. 22 Product specification SAA7110; SAA7110A 64 128 (1) YUV 2/LLC 176 2/LLC 4/LLC 118 2/LLC 2/LLC 97 MGC830 ...
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... Hz) UVn V634 1995 Oct ONE BUS CYCLE 764 765 766 U764 V764 U766 636 637 638 U636 V636 U638 Fig.12 HREF timing. 23 Product specification SAA7110; SAA7110A END OF ACTIVE LINE 767 V766 639 V638 MGC831 ...
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... Fig.13 Vertical timing. 24 Product specification SAA7110; SAA7110A 533 2/LLC 2 2/LLC 318 319 320 321 61 2/LLC 2 2/LLC 441 2/LLC 2 2/LLC 268 ...
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... YUV ( active Z transmitted once per line HPLL-INCR. FSCPLL-INCR Fig.15 Real time control output timing. 25 Product specification SAA7110; SAA7110A from 3-state t PD MGC833 SEQUENCE RESERVED ...
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... LLC2 LLC4 LLC4 26 Product specification SAA7110; SAA7110A PIXEL BYTE SEQUENCE FORMAT ...
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... Fig.16 YUV output signal range. XTALO 65 SAA7110 SAA7110A XTALI /-20 with external clock. Fig.17 Oscillator application. 27 Product specification SAA7110; SAA7110A 255 red 100% 240 212 red 75% 128 V-COMPONENT cyan 75% 44 cyan 100 MGC835 c. Y output range (R Y). ...
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... FC = LLC/4 1995 Oct 18 Table 4 System clock frequencies CLOCK XTAL LLC LLC2 LLC4 LLC8 ZERO PHASE CROSS DETECTION DETECTION Fig.18 Clock generation circuit. 28 Product specification SAA7110; SAA7110A FREQUENCY (MHz 26.8 29.5 24.545454 14.75 12.272727 7.375 6.136136 3.6875 3.068181 LOOP OSCILLATOR LLC FILTER DIVIDER ...
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... CLOCK CLOCK I/O OUTPUT CONTROL ACTIVE CONTROL Fig.19 Power-on control circuit. PIN OUTPUT STATUS 29 Product specification SAA7110; SAA7110A RESET MGC838 FUNCTION direct switching to high impedance (outputs) or input mode (I/Os) for 20 to 200 ms 2 starting I C-bus reset sequence SA0DH = 7DH (VTRC = 0, RTSE = 1, HRMV = 1, SSTB = 0, SECS = 1) ...
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... order to read (the circuit is slave transmitter) 9CH for write, 9DH for read ( 9EH for write, 9FH for read ( 00H to 19H decoder part 1AH to 1FH reserved 20H to 34H front-end part 30 Product specification SAA7110; SAA7110A ACK DATA (n bytes) DESCRIPTION ACK P ...
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... XXX XXX XXX 11 143 142 141 CHCV7 CHCV6 CHCV5 12 151 150 149 SATN7 SATN6 SATN5 31 Product specification SAA7110; SAA7110A (2) DATA BYTE 004 003 002 001 IDEL4 IDEL3 IDEL2 IDEL1 012 011 010 009 HSYB4 HSYB3 HSYB2 ...
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... IGAI1 IGAI0 GAI45 2C 103 102 101 CLS4 XXX CLS3 2D 111 110 109 IVAL7 IVAL6 IVAL5 32 Product specification SAA7110; SAA7110A (2) DATA BYTE 156 155 154 153 CONT4 CONT3 CONT2 CONT1 164 163 162 161 HS6B4 HS6B3 HS6B2 HS6B1 ...
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... Subaddresses to be reset 7DH, 0E and 31 to 00H after RESET = 0 (CGCE = 0) or power-on (CGCE = 1). 2. All reserved XXX-bits must be set to LOW, XX-bit is don’t care. 3. AFCCS bit does not exist in SAA7110A due to advanced anti-alias filter characteristic, don’t care (XX). Table 8 OCF1 ...
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... The horizontal PLL does not operate in this condition. The system clock frequency is set to a value fixed by the last update and is within 7.1% of the nominal frequency. 1995 Oct 18 DESCRIPTION 007 to 000) IDEL7 IDEL6 IDEL5 (2) 34 Product specification SAA7110; SAA7110A (1) CONTROL BITS IDEL4 IDEL3 IDEL2 IDEL1 IDEL0 ...
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... HCLB7 HCLB6 HCLB5 HCLB4 HCLB3 HCLB2 HCLB1 HCLB0 039 to 032) HCLS7 HCLS6 HCLS5 HCLS4 HCLS3 HCLS2 HCLS1 HCLS0 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS ...
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... Oct 18 047 to 040) HPHI7 HPHI6 HPHI5 Product specification SAA7110; SAA7110A CONTROL BITS HPHI4 HPHI3 HPHI2 HPHI1 ...
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... CONTROL BITS HUEC6 HUEC5 HUEC4 Product specification SAA7110; SAA7110A CONTROL BITS APER1 = 0; APER0 = 0 APER1 = 0; APER0 = 1 APER1 = 1; APER0 = 0 APER1 = 1; APER0 = 1 CORI1 = 0; CORI0 = 0 CORI1 = 0; CORI0 = 1 CORI1 = 1; CORI0 = 0 CORI1 = 1; CORI0 = 1 BPSS1 = 0; BPSS0 = 0 BPSS1 = 0; BPSS0 = 1 BPSS1 = 1; BPSS0 = 0 BPSS1 = 1; BPSS0 = 1 PREF = 0 ...
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... PLSE5 PLSE4 095 to 088) CONTROL BITS SESE6 SESE5 SESE4 Product specification SAA7110; SAA7110A CONTROL BITS CKTQ3 CKTQ2 CKTQ1 CONTROL BITS CKTS3 CKTS2 CKTS1 ...
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... HL switched to output pin 39 VL switched to output pin 40 TV/VCR mode select (VTRC); data bit D7 TV mode VTR mode 1995 Oct 18 103 to 096) 111 to 104) 39 Product specification SAA7110; SAA7110A CONTROL BITS LFIS1 = 0; LFIS0 = 0 LFIS1 = 0; LFIS0 = 1 LFIS1 = 1; LFIS0 = 0 LFIS1 = 1; LFIS0 = 1 COLO = 0 COLO = 1 CONTROL BITS ...
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... Hz, 625 lines 60 Hz, 525 lines Automatic field detection(AUFD); data bit D7 Field state directly controlled via FSEL Automatic field detection 1995 Oct 18 119 to 112) 127 to 120) 40 Product specification SAA7110; SAA7110A CONTROL BITS GPSW = 0 GPSW = 1 CHRS = 0 CHRS = 1 OEYC = 0 OEYC = 1 OEHV = 0 OEHV = 1 ...
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... CONTROL BITS SATN6 SATN5 SATN4 Product specification SAA7110; SAA7110A CONTROL BITS VNOI1 = 0; VNOI0 = 0 VNOI1 = 0; VNOI0 = 1 VNOI1 = 1; VNOI0 = 0 VNOI1 = 1; VNOI0 = 1 HRFS = 0 HRFS = 1 CHCV3 CHCV2 CHCV1 SATN3 ...
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... HS6S7 HS6S6 HS6S5 183 to 176) HC6B7 HC6B6 HC6B5 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS HS6B4 HS6B3 HS6B2 HS6B1 ...
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... BRIG7 BRIG6 BRIG5 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS HP6I4 HP6I3 HP6I2 HP6I1 ...
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... Analog input disable 3 (AIND3); data bit D6 Analog inputs 3 enabled Analog inputs 3 disabled Analog input disable 4 (AIND4); data bit D7 Analog inputs 4 enabled Analog inputs 4 disabled 1995 Oct 18 007 to 000) 44 Product specification SAA7110; SAA7110A CONTROL BITS AINS2 = 0 AINS2 = 1 AINS3 = 0 AINS3 = 1 AINS4 = 0 AIND4 = 1 FUSE1 = 0; FUSE0 = 0 FUSE1 = 0; FUSE0 = 1 FUSE1 = 1 ...
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... MUXC select channel 34 (MS34); data bit D6 Analog MUX3 controlled by MX34 Analog MUX3 controlled by MUXC Vertical blanking control off (VBCO); data bit D7 Vertical blanking on Vertical blanking off 1995 Oct 18 015 to 008) 45 Product specification SAA7110; SAA7110A CONTROL BITS REFS2 = 0 REFS2 = 1 REFS3 = 0 REFS3 = 1 REFS4 = 0 REFS4 = 1 MS24 = 0 MS24 = 1 MX241 = 0 ...
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... CONTROL BITS CLL216 CLL215 CLL214 Product specification SAA7110; SAA7110A CONTROL BITS MX341 = 0; MX340 = 0 MX341 = 0; MX340 = 1 MX341 = 1; MX340 = 0 MX341 = 1; MX340 = 1 CLTS = 0 CLTS = 1 MUYC = 0 MUYC = 1 YSEL = 0 YSEL = 1 CSEL = 0 CSEL = 1 GACO1 = 0; GACO0 = 0 GACO1 = 0; GACO0 = 1 GACO1 = 1; GACO0 = 0 GACO1 = 1; GACO0 = 1 ...
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... CONTROL BITS CLL326 CLL325 CLL324 Product specification SAA7110; SAA7110A CLL223 CLL222 CLL221 CLL313 CLL312 CLL311 ...
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... CONTROL BIT HOLD 071 to 064) WIPE7 WIPE6 WIPE5 079 to 072) SBOT7 SBOT6 SBOT5 Product specification SAA7110; SAA7110A #1 CONTROL BITS GAI22 GAI21 CONTROL BITS WIPE4 ...
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... GAIN CONTROL ANALOG GAIN GAI45 GAI44 2. Product specification SAA7110; SAA7110A #2 CONTROL BITS GAI33 GAI32 GAI31 CONTROL BITS IWIP1 = 0; IWIP0 = 0 IWIP1 = 0; IWIP0 = 1 IWIP1 = 1 ...
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... VBPS7 VBPS6 VBPS5 VBPS4 VBPS3 VBPS2 VBPS1 VBPS0 Product specification SAA7110; SAA7110A CONTROL BITS TWO2 = 0 TWO2 = 1 TWO3 = 0 TWO3 = 1 CLS2 = 0 CLS2 = 1 CLS3 = 0 CLS3 = 1 CLS4 = 0 CLS4 = 1 CONTROL BITS IVAL4 IVAL3 IVAL2 IVAL1 0 0 ...
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... Fix value integration 1995 Oct 18 127 to 120) VBPR7 VBPR6 VBPR5 VBPR4 VBPR3 VBPR2 VBPR1 VBPR0 135 to 128) 51 Product specification SAA7110; SAA7110A CONTROL BITS CONTROL BITS GAD21 = 0; GAD20 = 0 GAD21 = 0; GAD20 = 1 GAD21 = 1; GAD20 = 0 GAD21 = 1; GAD20 = 1 ...
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... AOSL1 = 0; AOSL0 = 0 AOSL1 = 0; AOSL0 = 0 AOSL1 = 1; AOSL0 = 1 AOSL1 = 1; AOSL0 = 1 151 to 144) WVAL7 WVAL6 WVAL5 WVAL4 WVAL3 WVAL2 WVAL1 WVAL0 Product specification SAA7110; SAA7110A CONTROL BITS PULIO = 0 PULIO = 1 VBLKA = 0 VBLKA = 1 SQPB = 0 SQPB = 1 WRSE = 0 WRSE = 1 WRIS = 0 WRIS = 1 CONTROL BITS 0 0 ...
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... LLC cycle phase delay for CLAA path 1995 Oct 18 159 to 152) 167 to 160) UPDATE NEW GAIN - OLD GAIN GUDL5 GUDL4 GUDL3 GUDL2 GUDL1 GUDL0 >0 0 >7 0 always 1 53 Product specification SAA7110; SAA7110A CONTROL BITS CAD2 = 0 CAD2 = 1 CAD3 = 0 CAD3 = 1 CHSB = 0 CHSB = 1 OFTS = 0 OFTS = 1 CONTROL BITS ...
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... CVBS6 5 AD3 AD2 Fig.21 Mode 0; CVBS1. 54 Product specification SAA7110; SAA7110A CLS3 clamp up/down CLL32 CLAMP CON3 CLL31 MX340 ADC3 CHRS v BYPS MX341 CSEL MX240 YSEL ADC2 MX241 CLS2 CLL22 clamp up/down CLAMP CON2 ...
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... AI21 AI22 1995 Oct 18 AD3 AD2 Fig.22 Mode 1; CVBS2. AD3 AD2 Fig.23 Mode 2; CVBS3. AD3 AD2 Fig.24 Mode 3; CVBS4. AD3 AD2 Fig.25 Mode 4; CVBS5. 55 Product specification SAA7110; SAA7110A CHROMA LUMA MGC841 CHROMA LUMA MGC842 CHROMA LUMA MGC843 CHROMA LUMA MGC844 ...
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... AI22 1995 Oct 18 AD3 AD2 Fig.26 Mode 5; CVBS6. AD3 AD2 Fig.27 Mode C1. AD3 AD2 Fig.28 Mode C2. AD3 AD2 Fig.29 Mode C3. 56 Product specification SAA7110; SAA7110A CHROMA LUMA MGC845 CHROMA LUMA MGC846 CHROMA LUMA MGC847 CHROMA LUMA MGC848 ...
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... BAH B8H 7CH 78H 05H 05H 03H 03H 57 Product specification SAA7110; SAA7110A ...
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... Hz. 1995 Oct 18 MODE 91H 91H D2H 03H 03H 83H 0XXXXXXX 60H 60H 60H Fig.30 Anti-alias filter graph for SAA7110A. 58 Product specification SAA7110; SAA7110A D2H 42H B1H C1H 83H A3H 13H 23H 1XXXXXXX 60H 44H 60H 44H ...
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... Y2) with respect to the 8-bit luminance output. Table 65 CORI control settings a, b and c of Fig.32 CONTROL BITS CORI1 1995 Oct 18 (2) (4) ( Fig.31 Anti-alias filter graph for SAA7110. handbook, halfpage CORI0 Product specification SAA7110; SAA7110A ( ...
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... Fig.34 Luminance control: SU06H, 50 Hz/CVBS mode, prefilter on and coring off (40 to 43H). 1995 Oct 43H 42H 41H 40H Product specification SAA7110; SAA7110A MGC852 43H 53H 73H 63H 40H (MHz) MGC853 43H 42H 41H 40H 6 ...
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... VY (dB Fig.36 Luminance control: SU06H mode, prefilter off and coring off. 1995 Oct 83H 82H 81H 80H Product specification SAA7110; SAA7110A MGC854 03H 13H 33H 23H 00H (MHz) MGC855 (MHz) ...
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... Fig.38 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter on and coring off. 1995 Oct 18 C3H C2H C1H C0H Product specification SAA7110; SAA7110A MGC856 (MHz) MGC857 43H 53H 73H 63H 40H (MHz ...
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... Fig.40 Luminance control: SU06H, 60 Hz/CVBS mode, prefilter off and coring off. 1995 Oct 18 43H 42H 41H 40H Product specification SAA7110; SAA7110A MGC858 43H 42H 41H 40H (MHz) MGC859 03H 13H 33H 23H 00H (MHz) ...
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... Fig.41 Luminance control: SU06H mode, prefilter off and coring off. 18 handbook, full pagewidth VY (dB Fig.42 Luminance control: SU06H mode, prefilter on and coring off. 1995 Oct 18 83H 82H 81H 80H 2 4 C3H C2H C1H C0H Product specification SAA7110; SAA7110A MGC860 (MHz) MGC861 (MHz) Y ...
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... Hz horizontal sync (HSY) stop 60 Hz horizontal clamp (HCL) begin horizontal clamp (HCL) stop 60 Hz horizontal sync after PHI1 60 Hz luminance brightness 65 Product specification SAA7110; SAA7110A BINARY ...
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... SET vertical blanking pulse RESET ADCs gain control mixer control #3 integration value white peak mixer control #4 gain update level 66 Product specification SAA7110; SAA7110A BINARY ...
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... XTALO 66 XTALI C18 SSA V SS Fig.43 Application diagram. 67 SAA7110; SAA7110A V DD1 C15 100 nF C14 V DD2 100 nF V DD3 C13 100 nF V DD4 C12 100 nF V DD5 C11 V SS 100 ...
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... SSA V DDA V DDD The OCF1 supports for special applications the use of an external CGC (SAA7197). For normal operation the built-in CGC fulfils all requirements. Fig.44 Application diagram with external Clock Generator Circuit (CGC). SAA7110 SAA7110A ...
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... B&W50? yes no B&W60? yes NTSC? no NTSC set-up B&W60 set-up stop Fig.45 Software flow example. 69 Product specification SAA7110; SAA7110A mode 0 set-up precharge clamping capacitor mode B&W50? yes XX0XXX00 B&W60? yes XX1XXX00 NTSC? yes XX1XXXXX SECAM? yes XX0XXX01 no PAL set-up yes ...
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... SUB 11 WRITE 59 !CHCV SUB 2E WRITE 9A !VBPS PAUSE %150 !150ms IF 1 @XX0XXX01 THEN GOTO SECAM ELSE PRINT "PAL" GOTO STOP 1995 Oct 18 SAA7110; SAA7110A #SECAM SUB 0D WRITE 07 !SECS -> 1 PRINT "SECAM" GOTO STOP #STOP 23.2 MODE 0 Source Select Procedure SLAVE 9C !OCF1 SUB 06 WRITE 00 ...
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... SUB 06 WRITE 80 !Y+C MODE 8 SUB 20 WRITE 3C !AI41=Y, AI32=C SUB 21 WRITE 27 !REFS ON SUB 22 WRITE C1 !AD2->LUMA, AD3->CHR 1995 Oct 18 SAA7110; SAA7110A SUB 2C WRITE 23 !CLAMP SELECT SUB 30 WRITE 44 !Gain AD2 active SUB 31 WRITE 75 !AOSL -> 01 SUB 21 WRITE 21 !REFS OFF CLAMP AKTIV 71 Product specification ...
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... scale (1) ( 0.81 24.33 24.33 23.62 23.62 1.27 0.66 24.13 24.13 22.61 22.61 0.032 0.958 0.958 0.930 0.930 0.05 0.026 0.950 0.950 0.890 0.890 REFERENCES JEDEC EIAJ MO-047AC 72 SAA7110; SAA7110A detail max. 25.27 25.27 1.22 1.44 0.51 0.18 0.18 25.02 25.02 1.07 1.02 0.995 ...
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... C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes 1995 Oct 18 SAA7110; SAA7110A 25.3 Wave soldering Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 1995 Oct 18 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 74 Product specification SAA7110; SAA7110A 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors One Chip Front-end 1 (OCF1) 1995 Oct 18 SAA7110; SAA7110A NOTES 75 Product specification ...
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Philips Semiconductors – a worldwide company Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, ...