at40kel040 ATMEL Corporation, at40kel040 Datasheet

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at40kel040

Manufacturer Part Number
at40kel040
Description
Rad Hard Reprogrammable Fpgas With Freeram
Manufacturer
ATMEL Corporation
Datasheet
Features
SRAM based FPGA Dedicated to Space Use
SEE Hardened Cells (configuration RAM, FreeRAM, DFF, JTAG, I/O buffers) Remove the
need for Triple Modular Redundancy (TMR)
Produced on Rad Hard 0.35µm CMOS Process
Functionally and Pin Compatible with the Atmel Commercial and Military AT40K Series
High Performance
FreeRAM
8 Global Clocks and 4 Additional Dedicated PCI Clocks
Global Reset Option
384 PCI Compliant I/Os
Package Options
Design Software (System Designer)
Supply Voltage 3.3V
AT40KFL040 is a 5V Tolerant Version
No Single Event Latch-up below a LET Threshold of 70 MeV/mg/cm2
Tested up to a Total Dose of 300 krads (Si) according to MIL STD 883 Method 1019
Quality Grades
Design Kit (AT40KEL-DK) Including:
Easy Migration to Atmel Gate Arrays for High Volume Production
– 46K Available ASIC gates (50% typ. routable)
– 60 MHz Internal Performance
– 20 MHz System Performance
– 30 MHz Array Multipliers
– 18 ns FreeRAM
– Internal Tri-state Capability in Each Cell
– 18432 Bits of Distributed SRAM Independent of Logic Cells
– Flexible, Single/Dual Port, Synchronous/Asynchronous 32x4 RAM blocks
– Fast, Low Skew Clock Distribution
– Programmable Rising/Falling Edge Transitions
– Distributed Clock Shutdown Capability for Low Power Management
– Programmable Output Drive
– Fast, Flexible Array Access Facilitates Pin Locking
– MQFPF160
– MQFPF256
– Combination of Atmel internally developed tools, and industry standard design
– Fast and Efficient Synthesis
– Efficient Integration (Libraries, Interface, Full Back-annotation)
– Over 75 Automatic Component Generators Create Thousands
– Automatic/Interactive Multi-chip Partitioning
– QML -Q and -V with SMD 5962-03250
– ESCC with 9304/008
– A Board with the RH FPGA (MQFPF160 or MQFPF256)
– A configuration memory (AT17 Atmel EEPROM)
– Design software and documentation
– ISP cable and software
tools
of Speed and Area Optimized Logic and RAM Functions
access time
Note:
All
AT40KEL040 in this document, also apply to the
AT40KFL040 unless specified otherwise.
features
and
characteristics
described
for
Reprogrammable
FPGAs with
FreeRAM
Rad Hard
AT40KEL040
AT40KFL040
4155I–AERO–06/06

Related parts for at40kel040

at40kel040 Summary of contents

Page 1

... Design software and documentation – ISP cable and software • Easy Migration to Atmel Gate Arrays for High Volume Production Note: All features and characteristics AT40KEL040 in this document, also apply to the AT40KFL040 unless specified otherwise. Rad Hard Reprogrammable FPGAs with FreeRAM AT40KEL040 AT40KFL040 described for 4155I– ...

Page 2

... The AT40KEL040 FPGA offers a patented distributed 18 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’ ...

Page 3

... This is the reason why Atmel proposes a 1Mbit serial EEPROM for configuring the AT40KEL040, the AT17LV010-10DP which is also a 3.3V bias chip packaged into a 28-pin DIL Flat Pack 400mils wide. This memory has been tested for total dose under bias and unbiased conditions, exhib- iting far better results when unbiased ...

Page 4

... The Symmetrical Array AT40KEL040 4 At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous from one edge to the other, except for bus repeaters spaced every four cells (Figure 2 on page 5). At the intersection of each repeater row and col- umn RAM block accessible by adjacent buses ...

Page 5

RAM RAM RAM RAM RV RV 4155I–AERO–06/06 Figure 2. Floorplan (Representative Portion) = Core Cell RAM ...

Page 6

... Express/Express turns are implemented through separate pass gates distributed throughout the array. Some of the bus resource on the AT40KEL040 is used as a dual-function resource. Table 2 shows which buses are used in a dual-function mode and which bus plane is used. The AT40KEL040 software tools are designed to accommodate dual-function buses in an efficient manner ...

Page 7

... Figure 3. Busing Plane (One of Five) 4155I–AERO–06/06 AT40KEL040 = AT40K/40KAL = Local/Local or Express/Express Turn Point = Row Repeater = Column Express Express bus bus Local bus 7 ...

Page 8

... CEL CEL CEL CEL (a) Cell-to-cell Connections AT40KEL040 8 Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). ...

Page 9

... This allows bus signals to switch planes to achieve greater routability five simultaneous local/local turns are possible. The AT40KEL040 FPGA core cell is a highly configurable logic block based around two 3-input LUTs ( ROM), which can be combined to produce one 4-input LUT. This means that any core cell can implement two functions of 3 inputs or one function of 4 inputs ...

Page 10

... SUM Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40KEL040 core cell or can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the SUM (Registered) sum output in this diagram is registered ...

Page 11

RAM 4155I–AERO–06/ dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sec- tor rows (plane 1). A 4-bit Output ...

Page 12

... RAM-Clear Byte Figure 9 on page 13 shows an example of a RAM macro constructed using AT40KEL040’s FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchro- nous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells (core cells) in the sectors occu- pied by the RAM will be unused: they can be used for other logic in the design ...

Page 13

Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) 4155I–AERO–06/06 13 ...

Page 14

... Clocking Scheme AT40KEL040 14 There are eight Global Clock buses (GCK1 - GCK8) on the AT40KEL040 FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. ...

Page 15

Figure 10. Clocking (for One Column of Cells) Express Bus (Plane 4; Half length at edge) 4155I–AERO–06/06 “1” Sector Clock Mux Global Clock Line (Buried) “1” Repeater Sector Clock Mux “1” “1” FCK (2 per Edge Column of the Array) ...

Page 16

... Set/Reset Scheme AT40KEL040 16 The AT40KEL040 family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources ...

Page 17

Figure 11. Set/Reset (for One Column of Cells) Repeater Express Bus (Plane 5; Half length at edge) 4155I–AERO–06/06 Each Cell has a programmable Set or Reset Sector Set/Reset Mux “1” Global Set/Reset Line (Buried) “1” “1” “1” Any User I/O ...

Page 18

... The Source Selection mux selects the source for the output signal of an I/O. See Figure 12 on page 21. The AT40KEL040 has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40KEL040 has access to one Primary I/O and two Secondary I/Os. Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and from a Primary I/O cell ...

Page 19

... Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KEL040 FPGA with core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing net- works running along the edges of the array ...

Page 20

... Figure 12. South I/O (Mirrored for North I/O) AT40KEL040 20 (a) Primary I/O (a) Primary I/O (b) Secondary I/O 4155I–AERO–06/06 ...

Page 21

Figure 13. West I/O (Mirrored for East I/O) PULL-UP PAD PULL-DOWN 4155I–AERO–06/06 a. Primary I/0 "0" "1" "0" "1" b. Secondary I/O CELL CELL 21 ...

Page 22

... Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners) VCC DRIVE TRI-ST ATE RST PULL-UP PAD PULL-DOWN AT40KEL040 22 PAD VCC GND DRIVE TTL/CMOS TRI-ST ATE SCHMITT DELAY ICLK OCLK RST RST "0" "1" "0" "1" PAD GND TTL/CMOS SCHMITT DELAY ICLK ...

Page 23

Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65°C to +150°C Junction Temperature .................................................. +150°C Voltage on Any Input Pin (1) with Respect to Ground ......-0.5V to 5.5V DC (KEL version) ................................................ -0.5V to ...

Page 24

... High-level Tri-state Output I OZH Leakage Current Low-level Tri-state Output I OZL Leakage Current I Standby Current CC Consumption (1) C Input Capacitance IN Note: 1. Parameter based on characterization and simulation not tested in production. Power-On Supply Requirements AT40KEL040 24 Conditions CMOS TTL CMOS TTL ...

Page 25

AC Timing Characteristics Delays are based on fixed loads which are described in the notes. Maximum timing based on worst case: V Minimum timing based on best case: V Maximum delays are the average of t Cell Function Parameter Core ...

Page 26

... PD Output, slow t PZX Output, slow t PXZ Output, medium t PZX Output, medium t PXZ Output, fast t PZX Output, fast t PXZ AT40KEL040 26 Path (max) pad -> x/y (max) pad -> x/y (max) pad -> x/y (max) pad -> x/y (max) x/y/E/L -> pad (max) x/y/E/L -> pad (max) x/y/E/L -> pad (max) oe -> pad (max) oe -> pad (max) oe -> ...

Page 27

AC Timing Characteristics Clocks and Reset Input buffers are measured from a V Maximum timings for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function Parameter Global Clocks and Set/Reset GCK Input buffer t ...

Page 28

... PD Write/Read t (max) PD Read t (max) PD Read t (max) PZX Read t (max) PXZ AT40KEL040 28 Path Value cycle time addr setup -> addr hold -> we din setup -> we din hold -> hold -> we din -> dout rd addr -> dout oe -> dout oe -> dout cycle time clk clk we setup -> ...

Page 29

FreeRAM Asynchronous Timing Characteristics Single Port Write/Read Dual Port Write with Read Dual Port Read 4155I–AERO–06/06 29 ...

Page 30

... FreeRAM Synchronous Timing Characteristics Single Port Write/Read CLK WE ADDR OE DATA Dual Port Write with Read CLK WE WR ADDR WR DATA RD ADDR = WR ADDR 1 RD DATA AT40KEL040 30 t CLKH t t WCS WCH t t ACS ACH OXZ t t DCS DCH t CLKH t t WCH WCS ...

Page 31

Dual Port Read RD ADDR OE DATA 4155I–AERO–06/ OZX OXZ 31 ...

Page 32

... Table 4. MQFP F-160 Pin Number AT40KEL040 32 Pin Number Signal 34 I/O297_CS1_A2 VCC 35 I/O384_GCK8_A15 36 I/O383_A14 37 I/O290_GCK7_A1 I/O382 38 I/O381 39 I/O372_A13 40 I/O371_A12 41 I/O370 42 I/O369 43 GND 44 I/O360 45 I/O359 46 I/O348_A11 47 I/O347_A10 48 ...

Page 33

... AT40KEL040 33 Pin Signal Number I/O144_INIT 136 I/O143_D15 137 I/O138 138 I/O137 139 I/O124 140 I/O123 141 I/O122 142 I/O121 143 ...

Page 34

... Table 5. MQFP - F256 Pin Number AT40KEL040 34 Pin Number Signal 34 IO384_GCK8_A15 35 IO383_A14 36 IO382 37 IO381 38 IO378 39 IO377 40 GND 41 VCC 42 IO375 43 IO374 44 IO372_A13 45 IO371_A12 46 IO370 47 IO369 48 IO366 49 IO365 ...

Page 35

... AT40KEL040 35 Pin Signal Number IO234 136 IO232 137 IO184_D9 IO230 138 IO183_D10 IO228 139 IO227 140 IO225 141 IO224 142 ...

Page 36

... AT40KEL040 36 Pin Signal Number IO85 238 IO84 239 IO28_A21 IO83 240 IO27_A20 IO80 241 IO79 242 IO25_FCK1 IO77 243 IO76 ...

Page 37

... Part/Package Availability and User I/O Counts (Including Dual-function Pins) 4155I–AERO–06/06 Package MQFPF 160 MQFPF 256 AT40KEL040 129 233 37 ...

Page 38

... Ordering Information Part Number AT40KEL040KW1-E 5962-0325001QXC 5962-0325001VXC 930400801 AT40KEL040KZ1-E 5962-0325001QYC 5962-0325001VYC 930400802 AT40KFL040KW1-E 5962-0325002QXC 5962-0325002VXC AT40KFL040KW1-SCC AT40KFL040KZ1-E 5962-0325002QYC 5962-0325002VYC AT40KFL040KZ1-SCC AT40KEL040 38 Package Version MQFPF160 3.3V MQFPF160 3.3V MQFPF160 3.3V MQFPF160 3.3V MQFPF256 3.3V MQFPF256 3.3V MQFPF256 3.3V MQFPF256 3.3V MQFPF160 3.3V, 5V Tolerant MQFPF160 3.3V, 5V Tolerant MQFPF160 3.3V, 5V Tolerant MQFPF160 3.3V, 5V Tolerant MQFPF256 3.3V, 5V Tolerant MQFPF256 3 ...

Page 39

Package Drawing Multilayer Quad Flat Pack (MQFP) 160-pin - Front View 4155I–AERO–06/06 39 ...

Page 40

... Multilayer Quad Flat Pack (MQFP) 256-pin - Front View AT40KEL040 40 4155I–AERO–06/06 ...

Page 41

Datasheet Change Log Changes from 4155B - 06/03 to 4155C 04/04 Changes from 4155C - 06/03 to 4155D 04/04 Changes from 4155D 04/ 4155E 06/04 Changes from 4155E 06/04 to 4155F 06/04 Changes from 4155F 06/04 to 4155G ...

Page 42

... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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