ep2c35 Altera Corporation, ep2c35 Datasheet

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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. Altera Corporation Section I. Cyclone II Device Family Data Sheet Chapter 1. Introduction Chapter 2. Cyclone II Architecture Chapter 3. Configuration & ...

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... Revision History Section I–2 Preliminary Cyclone II Device Handbook, Volume 1 Altera Corporation ...

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... You can implement high-performance yet low-cost DSP systems with the following Cyclone II features and design support: ■ ■ ■ Altera Corporation February 2008 ® Cyclone II FPGAs extend the low-cost FPGA density Up to 150 18 × 18 multipliers Up to 1.1 Mbit of on-chip embedded memory High-speed interfaces to external memory 1 ...

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... Peripheral Component Interconnect Special Interest Group (PCI ● SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation MHz for 32- or 64-bit interfaces PCI Express with an external TI PHY and an Altera PCI Express ● ® ×1 Megacore function Altera Corporation February 2008 ...

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... Altera Corporation February 2008 133-MHz PCI-X 1.0 specification compatibility ● High-speed external memory support, including DDR, DDR2, ● and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use Three dedicated registers per I/O element (IOE): one input ● ...

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... EP2C8 (2) EP2C15 (1) EP2C20 8,256 14,448 18,752 165,888 239,616 239,616 www.altera.com to Automotive-Grade Device chapter in the Table 1–2 lists the (2) EP2C35 EP2C50 EP2C70 33,216 50,528 68,416 105 129 250 483,840 594,432 1,152, 150 Altera Corporation February 2008 ...

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... Altera Corporation February 2008 EP2C8 (2) EP2C15 (1) EP2C20 182 315 315 18 multipliers. For the total number of 9 Introduction (2) EP2C35 EP2C50 EP2C70 475 450 622 × 9 multipliers per device, multiply the Cyclone II Device Handbook, Volume 1 1–5 ...

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... The I/O pin counts for the EP2C5, EP2C8, and EP2C15A devices include 8 dedicated clock pins that can be used for data inputs. The I/O counts for the EP2C20, EP2C35, EP2C50, and EP2C70 devices include 16 dedicated clock pins that can be used for data inputs. (7) EP2C8A, EP2C15A, and EP2C20A have a Fast On feature that has a faster POR time ...

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... When migrating from the EP2C20F484 device to the EP2C50F484 device, a total of 39 I/O pins are non-migratable. (3) When migrating from the EP2C35F672 device to the EP2C70F672 device, a total of 56 I/O pins are non-migratable. (4) In addition to the one non-migratable I/O pin, there are 34 DQ pins that are non-migratable. ...

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... EP2C8A (2) — — EP2C15A — — EP2C20 — — EP2C20A (2) — — EP2C35 — — EP2C50 — — EP2C70 — — Notes to Table 1–4: (1) The EP2C5 optionally support the Fast On feature, which is designated with an “A” in the device ordering code. The EP2C5A is only available in the automotive speed grade. Refer to the Cyclone II section in the Device Handbook for detailed information ...

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... Updated Table v1.1 ● Updated bullet list in the June 2004 v1.0 Added document to the Cyclone II Device Handbook. Altera Corporation February 2008 Hot Socketing & Power-On Reset Automotive-Grade Device Handbook shows the revision history for this document. Changes Made Documents”. section and Table 1– ...

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... Document Revision History 1–10 Cyclone II Device Handbook, Volume 1 Altera Corporation February 2008 ...

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... Mbps for outputs. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to Altera Corporation February 2007 2. Cyclone II Architecture ® ...

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... A programmable register A carry chain connection A register chain connection The ability to drive all types of interconnects: local, row, column, register chain, and direct link interconnects Support for register packing Support for register feedback PLL Logic IOEs Array M4K Blocks PLL Altera Corporation February 2007 ...

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... LUT for unrelated functions. When using register packing, the LAB-wide synchronous load control signal is not available. See Altera Corporation February 2007 shows a Cyclone II LE. Register Chain ...

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... LUT. LEs in normal mode support packed registers and register feedback. 2–4 Cyclone II Device Handbook, Volume 1 “MultiTrack Interconnect” on page 2–10 Normal mode Arithmetic mode ® II software, in conjunction with parameterized functions for more Figure 2–3). The Altera Corporation February 2007 ...

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... arithmetic mode implements a 2-bit full adder and basic carry chain (see mode can drive out registered and unregistered versions of the LUT output. Register feedback and register packing are supported when LEs are used in arithmetic mode. Altera Corporation February 2007 sload sclear (LAB Wide) ...

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... Wide) (LAB Wide) Register chain connection D ENA clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) cout Register Feedback Row, column, and Q direct link routing Row, column, and direct link routing CLRN Local routing Register chain output Altera Corporation February 2007 ...

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... Figure 2–5 Figure 2–5. Cyclone II LAB Structure Direct link interconnect from adjacent block Direct link interconnect to adjacent block Altera Corporation February 2007 16 LEs LAB control signals LE carry chains Register chains Local interconnect shows the Cyclone II LAB. Local Interconnect LAB Cyclone II Architecture ...

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... Cyclone II Device Handbook, Volume 1 Local Two clocks Two clock enables Two asynchronous clears One synchronous clear One synchronous load Figure 2–6 Direct link interconnect from right LAB, M4K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect to right LAB Altera Corporation February 2007 ...

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... Interconnect Local Interconnect LAB-wide signals control the logic for the register’s clear signal. The LE directly supports an asynchronous clear function. Each LAB supports up to two asynchronous clear signals (labclr1 and labclr2). Altera Corporation February 2007 labclkena2 labclkena1 labclk1 labclk2 Cyclone II Device Handbook, Volume 1 Cyclone II Architecture ™ ...

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... These row resources include: ■ ■ ■ 2–10 Cyclone II Device Handbook, Volume 1 Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left R24 interconnects for high-speed access across the length of the device Altera Corporation February 2007 ...

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... Driving Left Notes to Figure 2–8: (1) C4 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. Altera Corporation February 2007 Figure 2–8 shows R4 interconnect connections from an LAB. Figure Adjacent LAB can Drive onto Another C4 Column Interconnects (1) LAB's R4 Interconnect ...

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... Cyclone II Device Handbook, Volume 1 Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks and down direction C16 interconnects for high-speed vertical routing through the device Figure 2–9 shows the register chain interconnects. Altera Corporation February 2007 ...

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... PLLs, M4K memory blocks, embedded multiplier blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor (see interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. Altera Corporation February 2007 Local Interconnect Routing Among LEs in the LAB ...

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... Figure 2–10: (1) Each C4 interconnect can drive either up or down four rows. 2–14 Cyclone II Device Handbook, Volume 1 Note (1) Primary Local LAB Interconnect C4 Interconnect Drives Local and R4 Interconnects Up to Four Rows C4 Interconnect Driving Up LAB LAB Neighbor C4 Interconnect Driving Down Altera Corporation February 2007 ...

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... Table 2–1. Cyclone II Device Routing Scheme (Part Source Register Chain Local Interconnect v Direct Link Interconnect v R4 Interconnect R24 Interconnect v C4 Interconnect C16 Interconnect Altera Corporation February 2007 shows the Cyclone II device’s routing scheme. Destination ...

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... Cyclone II Device Handbook, Volume 1 Destination global clock networks Up to four PLLs Global clock network dynamic clock source selection Global clock network dynamic enable and disable Altera Corporation February 2007 ...

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... Cyclone II device. CLK[] pins are dedicated clock pins and DPCLK[] pins are dual-purpose clock pins. Table 2–2. Cyclone II Device Clock Resources EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 EP2C70 Figures 2–11 inputs, DPCLK[] pins, and clock control blocks. Altera Corporation February 2007 ...

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... Clock Control Block (1) DPCLK0 CLK[3..0] 4 DPCLK1 4 PLL 1 DPCLK2 Note to Figure 2–11: (1) There are four clock control blocks on each side. 2–18 Cyclone II Device Handbook, Volume 1 DPCLK8 GCLK[7.. GCLK[7..0] DPCLK4 PLL 2 4 DPCLK7 CLK[7..4] 4 DPCLK6 Clock Control Block (1) Altera Corporation February 2007 ...

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... There are four clock control blocks on each side. Only one of the corner CDPCLK pins in each corner can feed the clock control block at a time. The other CDPCLK pins (2) can be used as general-purpose I/O pins. Altera Corporation February 2007 DPCLK[11..10] DPCLK[9..8] CLK[11..8] CDPCLK6 ...

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... TRDY and IRDY for PCI, or DQS signals for external memory interfaces. 2–20 Cyclone II Device Handbook, Volume 1 and 2–12. Figures 2–11 and 2–12). Altera Corporation February 2007 ...

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... The following sources can be inputs to a given clock control block: ■ ■ ■ ■ Altera Corporation February 2007 Dynamic global clock network clock source selection Dynamic enable/disable of the global clock network Four clock pins on the same side as the clock control block ...

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... Internal logic can be used to enabled or disabled the global clock network in user mode. 2–22 Cyclone II Device Handbook, Volume 1 Figure 2–13 shows a more detailed diagram of the Clock Control Block Internal Logic DPCLK or CDPCLK ( PLL C2 CLKSELECT[1..0] (2) Enable/ Global Disable Clock Static Clock Select (3) CLKENA (4) ) for the PLL. IN Altera Corporation February 2007 ...

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... The LAB row clocks also extend to the row I/O clock regions. IOE clocks are associated with row or column block regions. Only six global clock resources feed to these row and column regions. shows the I/O clock regions. Altera Corporation February 2007 Cyclone II Architecture Figure 2– ...

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... Cyclone II Device Handbook, Volume 1 Column I/O Clock Region IO_CLK[5..0] LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5..0] 6 Global Clock Network LAB Row Clocks labclk[5..0] 6 Column I/O Clock Region IO_CLK[5..0] I/O Clock Regions 6 6 Row I/O Clock Region IO_CLK[5..0] 6 I/O Clock Regions Altera Corporation February 2007 ...

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... Cyclone II devices contain either two or four PLLs. PLLs available for each Cyclone II device. Table 2–3. Cyclone II Device PLL Availability EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 EP2C70 Altera Corporation February 2007 Clock multiplication and division Phase shifting Programmable duty cycle Up to three internal clock outputs ...

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... The signal enables and disables the PLLs. The areset signal resets/resynchronizes the inputs for each PLL. The pfdena signal controls the phase frequency detector (PFD) output with a programmable gate. _OUT <#> pin. If the C2 output is not Altera Corporation February 2007 ...

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... The M4K memory blocks include input registers that synchronize Memory writes and output registers to pipeline designs and improve system performance. The output registers can be bypassed, but input registers cannot. Altera Corporation February 2007 shows a block diagram of the Cyclone II PLL ...

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... Table 2–5 in each Cyclone II device. Table 2–5. M4K Memory Capacity & Distribution in Cyclone II Devices EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 EP2C70 2–28 Cyclone II Device Handbook, Volume 1 4,608 RAM bits 250-MHz performance True dual-port memory Simple dual-port memory Single-port memory ...

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... Power-up condition Register clears Same-port read-during-write Mixed-port read-during-write Note to Table 2–6: (1) Maximum performance information is preliminary until device characterization. Altera Corporation February 2007 summarizes the features supported by the M4K memory. 250 MHz 4,608 4K × × × 4 512 × 8 512 × 9 256 × ...

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... A single clock or dual clock FIFO may be implemented in the M4K blocks. Simultaneous read and write from an empty FIFO buffer is not supported. Embedded Memory can be inferred in your HDL code or directly instantiated in the Quartus II software using the ® MegaWizard Plug-in Manager Memory Compiler feature. Description Altera Corporation February 2007 ...

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... LAB and another 16 possible from the right adjacent LAB. M4K block outputs can also connect to left and right LABs through each 16 direct link interconnects. array interface. Altera Corporation February 2007 summarizes the different clock modes supported by the M4K Description In this mode, a separate clock is available for each port (ports A and B) ...

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... Cyclone II Device Handbook, Volume 1 dataout M4K RAM Block Byte enable Control Signals Clocks address datain LAB Row Clocks One 18-bit multiplier Up to two independent 9-bit multipliers R4 Interconnects Direct link interconnect to adjacent LAB 16 Direct link interconnect from adjacent LAB 6 Altera Corporation February 2007 ...

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... Table 2–10. Number of Embedded Multipliers in Cyclone II Devices Embedded Device Multiplier Columns EP2C5 1 EP2C8 1 EP2C15 1 EP2C20 1 EP2C35 1 EP2C50 2 EP2C70 3 Note to Table 2–10: (1) Each device has either the number of 9 × 9 × 18-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. ...

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... CLRN ENA CLRN D Q ENA Output Register Input Register CLRN Embedded Multiplier Block Table 2–11 shows the sign of the multiplication result for the Data B (signb Value) Unsigned Signed Unsigned Signed Data Out Result Unsigned Signed Signed Signed Altera Corporation February 2007 ...

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... Multiplier Modes Table 2–12 multipliers can operate in. Table 2–12. Embedded Multiplier Modes 18-bit Multiplier 9-bit Multiplier Altera Corporation February 2007 summarizes the different modes that the embedded Multiplier Mode An embedded multiplier can be configured to support a single 18 × 18 multiplier for operand widths bits. ...

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... R4 Interconnects Embedded Multiplier Control 36 [35..0] 18 Row Interface Block 36 Inputs per Row 36 Outputs per Row 18 Direct Link Outputs Direct Link Interconnect to Adjacent LABs from Adjacent LAB 36 18 LAB [35..0] 18 LAB Block Interconect Region C4 Interconnects Altera Corporation February 2007 ...

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... The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins. You can use IOEs as input, output, or bidirectional pins. Altera Corporation February 2007 Differential and single-ended I/O standards 3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance ...

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... Figure 2–20: There are two paths available for combinational or registered inputs to the logic array. Each path contains a unique programmable delay chain. shows how a row I/O block connects to the logic array. shows how a column I/O block connects to the logic array. Altera Corporation February 2007 ...

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... Each of the five IOEs in the row I/O block can have two io_datain (combinational or registered) inputs. Altera Corporation February 2007 C4 Interconnects I/O Block Local Interconnect 35 io_datain0[4 ...

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... Each of the four IOEs in the column I/O block can have two io_datain (combinational or registered) inputs. 2–40 Cyclone II Device Handbook, Volume 1 Column I/O Block io_datain0[3..0] 28 io_datain1[3..0] (2) LAB C4 & C24 Interconnects Column I/O Block Contains up to Four IOEs io_clk[5..0] LAB Altera Corporation February 2007 ...

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... Array io_caclr io_cclk io_dataout Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. selection. Altera Corporation February 2007 illustrates the signal paths through the I/O block. To Other IOEs oe ce_in ce_out Data and ...

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... LAB, dedicated I/O clocks, or the column and row interconnects. All registers share sclr and aclr, but each register can individually disable sclr and aclr. configuration. 2–42 Cyclone II Device Handbook, Volume 1 clk_out ce_out clk_in ce_in Figure 2–25 shows the IOE in bidirectional sclr/preset aclr/preset oe Altera Corporation February 2007 ...

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... Programmable delays decrease input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Altera Corporation February 2007 OE Register PRN ...

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... Cyclone II Device Handbook, Volume 1 Table 2–13 shows the programmable delays for Cyclone II Programmable Delays Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Quartus II Logic Option Altera Corporation February 2007 ...

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... For maximum performance, Altera recommends using the 1.8-V HSTL I/O standard because of higher I/O drive strength. QDRII SRAM devices also support the 1.5-V HSTL I/O standard. Cyclone II devices use data (DQ), data strobe (DQS), and clock pins to interface with external memory. in the ×8/×9 mode. Altera Corporation February 2007 Note (1) Maximum Clock Maximum Bus ...

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... Number of ×8 Number of ×9 Groups Groups (5 (3) 4 (3) ® ( (4) 8 (1), (2) DQ Pins DM Pin Number of ×16 Number of ×18 Groups Groups (5), ( Altera Corporation February 2007 ...

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... Table 2–15. Cyclone II DQS & DQ Bus Mode Support (Part Device Package EP2C35 484-pin FineLine BGA 672-pin FineLine BGA EP2C50 484-pin FineLine BGA 672-pin FineLine BGA EP2C70 672-pin FineLine BGA 896-pin FineLine BGA Notes to Table 2–15: (1) Numbers are preliminary. (2) EP2C5 and EP2C8 devices in the 144-pin TQFP package do not have any DQ pin groups in I/O bank 1. ...

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... DQS OE LE Register t LE Register DataA LE Register DataB LE Register Clock Delay Control Circuitry Global Clock en/dis Clock Control Dynamic Enable/Disable Circuitry Block ENOUT ena_register_mode DQ Adjacent LAB LEs LE LE Register Register Register Register Register Resynchronizing to System Clock Altera Corporation February 2007 ...

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... Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. the possible settings for the I/O standards with drive strength control. Table 2–16. Programmable Drive Strength (Part LVTTL (3.3 V) LVCMOS (3.3 V) LVTTL/LVCMOS (2.5 V) LVTTL/LVCMOS (1.8 V) Altera Corporation February 2007 I/O Standard Top & Bottom I/O Pins ...

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... Table 2–16: The default current in the Quartus II software is the maximum setting for each I/O standard. Note (1) Current Strength Setting (mA) Side I/O Pins Altera Corporation February 2007 ...

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... If you enable this feature for an I/O pin, the pull-up resistor (typically 25 kΩ) holds the output to the V level of the output pin’s bank. 1 Altera Corporation February 2007 If the bus-hold feature is enabled, the device cannot use the programmable pull-up option. Disable the bus-hold feature when the I/O pin is configured for differential signals ...

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... Side I/O Pins User I/O CLK, User I/O PLL_OUT Pins DQS Pins (2) (2) ( (2) (2) ( (2) (2) ( (6) v (7) v (6) Altera Corporation February 2007 ...

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... Cyclone II devices can transmit and receive data through LVDS signals at a data rate 640 Mbps and 805 Mbps, respectively. For the LVDS transmitter and receiver, the Cyclone II device’s input and output pins support serialization and deserialization through internal logic. Altera Corporation February 2007 Top & Bottom V ...

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... Cyclone II pin tables list the pins that support the high-speed I/O interface. The number of LVDS channels supported in each device family member is listed in Table 2–18. Cyclone II Device LVDS Channels (Part EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 2–54 Cyclone II Device Handbook, Volume 1 Table 2–18. Device Pin Count ...

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... This also minimizes the need for external resistors in high pin count ball grid array (BGA) packages. Cyclone II devices provide I/O driver on-chip impedance matching and on-chip series termination for single-ended outputs and bidirectional pins. Altera Corporation February 2007 Device Pin Count ...

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... I/O pins in order to enable on-chip series When using on-chip series termination, programmable drive strength is not available. Table 2–19 lists the I/O standards that Note (1) (Ω) V (V) S CCIO 25 (2) 3.3 50 (2) 2.5 (2) 50 1.8 (2) 50 2.5 50 (2) 1.8 ±50 mV. CCIO CCIO and V CCIO Altera Corporation February 2007 and S are REF ...

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... The top and bottom I/O banks (banks 2 and 4 in EP2C5 and EP2C8 devices and banks and 8 in EP2C15, EP2C20, EP2C35, EP2C50, and EP2C70 devices) support DDR2 memory up to 167 MHz/333 Mbps and QDR memory up to 167 MHz/668 Mbps. The left and right side I/O ...

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... Differential SSTL-2 (4) ■ Differential SSTL-18 (4) ■ Differential HSTL-18 (5) ■ Differential HSTL-15 (5) Individual Power Bus I/O Bank 4 I/O Bank 4 Also Supports the SSTL-18 Class II, HSTL-18 Class II, & HSTL-15 Class II I/O Standards I/O Bank 3 Also Supports the 3.3-V PCI & PCI-X I/O Standards I/O Bank 3 Altera Corporation February 2007 ...

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... Figure 2–29. EP2C15, EP2C20, EP2C35, EP2C50 & EP2C70 I/O Banks I/O Bank 2 I/O Banks 1 & 2 Also Support the 3.3-V PCI & PCI-X I/O Standards I/O Bank 1 Notes to Figure 2–29: (1) This is a top view of the silicon die. (2) This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations. ...

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... V value. REF CCIO level is 1.2 V, then input pins are 1.5-V, 1.8-V, 2.5-V, CCINT Note (1) 2.5 V 3 (2) ( (2) (2) ( (5) for CCIO is 3.3-V, a bank can CCIO pins CC Table 2–20 summarizes Output Signal 1.8 V 2 (5) Altera Corporation February 2007 ...

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... V (5) When V = 2.5-V, a Cyclone II device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs. CCIO (6) When V = 3.3-V, a Cyclone II device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs. CCIO Altera Corporation February 2007 Note (1) 2.5 V 3 ...

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... Changes Made 2–25. to Table 2–17. “I/O Banks” section. to Table 2–20. 2–7. and 2–12. 2–16. 2–18. 2–19. 2–16. Summary of Changes ● Removed Drive Strength Control from Figure 2–25. ● Elaboration of DDR2 and QDRII interfaces supported by I/O bank included. Altera Corporation February 2007 ...

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... TDI and TMS pins have weak internal pull-up resistors. The TDO output pin and all JTAG input pin voltage is determined by the V where it resides. The bank V 1.8-, 2.5-, or 3.3-V compatible. 1 Altera Corporation February 2007 3. Configuration & Testing ® II devices provide JTAG BST circuitry that complies with selects whether the JTAG inputs are 1 ...

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... File via an embedded processor. nCONFIG Emulates pulsing the pin low to trigger reconfiguration even though the physical pin is unaffected. Table 3–1. TDI TDO and pins serially shifted TDI TDO and , TDO . TDI TDO and pins, TDI TDO and pins, ™ or Altera Corporation February 2007 ...

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... If selected, the checksum is automatically loaded to the USERCODE register. In the Settings dialog box in the Assignments menu, click Device & Pin Options, then General, and then turn on the Auto Usercode option. Altera Corporation February 2007 Description Allows configuration of I/O standards through the JTAG chain for JTAG testing ...

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... Handbook, Volume 1. 3–4 Cyclone II Device Handbook, Volume 1 Tables 3–2 Device Boundary-Scan Register Length EP2C5 EP2C8 EP2C15 EP2C20 EP2C35 EP2C50 EP2C70 IDCODE (32 Bits) (1) Manufacturer Identity (11 Bits) 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 ...

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... CLKUSR pin during the initialization. The 10 MHz internal oscillator is disabled in user mode. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. Altera Corporation February 2007 Configuration & Testing Cyclone II Device Handbook, Volume 1 ® ...

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... Devices chapter of the Cyclone II Handbook, Volume 2. 3–6 Cyclone II Device Handbook, Volume 1 of the bank where the pins reside. The bank CCIO selects whether the configuration inputs are 1.5-V, 1.8-V, 2.5-V, or Table Data Source before CCIO 3–4), chosen on the basis of the Altera Corporation February 2007 ...

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... CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. f For more information on CRC, refer to AN: 357 Error Detection Using CRC in Altera FPGAs. Altera Corporation February 2007 Configuration & Testing Cyclone II Device Handbook, Volume 1 3–7 ...

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... Cyclone II Device Handbook, Volume 1 shows the revision history for this document. Changes Made “IEEE Std. 1149.1 (JTAG) section. Summary of Changes ● Added information about limitation of cascading multi devices in the same JTAG chain. ● Corrected information on CRC calculation. Altera Corporation February 2007 ...

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... Hot-Socketing requirements. The hot-socketing feature in Cyclone II devices offers the following: Specifications ■ ■ Altera Corporation February 2007 4. Hot Socketing & Power-On ® II devices offer hot socketing (also known as hot plug-in, hot Board or device insertion and removal without external components or board manipulation ...

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... I/O pin on the device. The DC supplies to the device are stable in the CC and simplify CCIO CCINT and V pins in CCIO CCINT must have monotonic rise CCINT Figure 4–3 for more supplies must CC | < 300 µA. IOPIN | < for IOPIN Altera Corporation February 2007 ...

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... These pins are expected to drive out during power-up and power-down sequences. Each I/O pin has the circuitry shown in Altera Corporation February 2007 to ground within the device result, the device extends supplies) or power down ...

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... Cyclone II device is powered before V CCIO CCINT . This also applies for sudden voltage spikes during hot CCIO leakage current charges the voltage tolerance control PAD Power-On Reset Monitor Hot Socket Output Pre-Driver or if the I/O pad voltage is higher Altera Corporation February 2007 ...

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... I/O pins until the V addition, the POR circuitry also monitors the V banks that contains configuration pins (I/O banks 1 and 3 for EP2C5 and EP2C8, I/O banks 2 and 6 for EP2C15A, EP2C20, EP2C35, EP2C50, and EP2C70) and tri-states all user I/O pins until the V recommended operating levels. After the Cyclone II device enters user mode, the POR circuit continues to monitor the V user mode can be detected ...

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... CC parameters will determine the initialization time. For more information on the t to the Configuring Cyclone II Devices chapter in the Cyclone II Device Handbook. Configuration Time Initialization Time CD2UM or t parameters, refer CD2UM CD2UMC Altera Corporation February 2007 Time User Mode ...

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... Added footnote to July 2005 v2.0 Updated technical content throughout. February 2005 Removed ESD section. v1.1 June 2004 v1.0 Added document to the Cyclone II Device Handbook. Altera Corporation February 2007 ramp time requirement, you must CC shows the revision history for this document. Changes Made section. Figure 4– ...

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... Document Revision History 4–8 Cyclone II Device Handbook, Volume 1 Altera Corporation February 2007 ...

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... During transitions, the inputs may overshoot to the voltage shown in The DC case is equivalent to 100% duty cycle. During transition, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Altera Corporation February 2008 5. DC Characteristics and Timing Specifications ® ...

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... Unit 1.15 1.25 V 3.135 (3.00) 3.465 (3.60) V (3) 2.375 2.625 V 1.71 1.89 V 1.425 1.575 °C –40 100 °C –40 125 °C –40 125 °C ) rise time is 100 ms for non-A devices Table 5–6, and those only applies to the PCI and PCI-X CCIO Altera Corporation February 2008 ...

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... EP2C35 EP2C50 EP2C70 V = ground, EP2C5 load, no EP2C8/A toggling inputs EP2C15A T = 25° 2.5 V EP2C20 EP2C35 EP2C50 EP2C70 Cyclone II Device Handbook, Volume 1 –0.5 — 4.0 V μA –10 — — μA –10 — ...

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... V are CCINT CCIO values may be different if V value is CONF IN . CCIO and maximum condition at CC overshoot voltage and the Table 5–3 Input Signal Duty Cycle 100% (DC) 90% 50% 30% 17% 10% Altera Corporation February 2008 kΩ kΩ kΩ kΩ kΩ kΩ CCIO for ...

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... SSTL-2 class I 2.375 2.5 SSTL-2 class II 2.375 2.5 SSTL-18 class I 1.7 1.8 Altera Corporation February 2008 DC Characteristics and Timing Specifications and 5–7 provide operating condition information when using Symbol Supply voltage for single-ended inputs and for output drivers Reference voltage for setting the input switching threshold ...

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... Voltage Thresholds (V) Minimum V ( 2.4 0.2 V – 0 0.4 2.0 V – 0. 0.75 × 0.9 × – 0. 0.57 TT – 0. 0.76 TT – 0.475 V + 0.475 TT V – 0. 0.4 V – 0 0.4 V – 0 Altera Corporation February 2008 ...

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... The LVDS I/O standard is supported on both receiver input pins and transmitter output pins. 1 Figure 5–1 standards (LVDS, LVPECL, differential 1.5-V HSTL class I and II, differential 1.8-V HSTL class I and II, differential SSTL-2 class I and II, and differential SSTL-18 class I and II). Altera Corporation February 2008 DC Characteristics and Timing Specifications I (mA) Maximum V OH – ...

Page 98

... The p – n waveform is a function of the positive channel (p) and the negative channel (n). 5–8 Cyclone II Device Handbook, Volume 1 V ( – n n)/2. ICM Positive Channel ( Negative Channel ( Ground 0 V (1) p − n (3) Altera Corporation February 2008 ...

Page 99

... The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock pins. (6) The LVPECL clock inputs are powered by V connect V to typical value of 3.3V. CCIO Altera Corporation February 2008 DC Characteristics and Timing Specifications shows the recommended operating conditions for user I/O V (V) (1) ...

Page 100

... V ( − n (3) Note (1) (Part ( Max Min Max Min 1.375 — — — 1.375 — — — 1.375 — — — — V — — – 0.4 Altera Corporation February 2008 Max — — — 0.4 ...

Page 101

... Table 5–10 Characteristics Table 5–10. Bus Hold Support for Different Pin Types I/O pins using single-ended I/O standards I/O pins using differential I/O standards Dedicated clock pins JTAG Configuration pins Altera Corporation February 2008 DC Characteristics and Timing Specifications ΔV (mV) V (V) OD OCM Max Min Max ...

Page 102

... Resistance Tolerance Extended/ Industrial Automotive Max Temp Max ±30 ±30 ±40 ±30 ±30 ±40 (1) ±40 ±50 Altera Corporation February 2008 Unit μA μA μA μA V Unit % % % ...

Page 103

... The exact amount of current consumed varies according to the process, temperature, and power ramp rate. The duration of the I V CCINT Altera Corporation February 2008 DC Characteristics and Timing Specifications shows the Cyclone II device pin capacitance for different I/O Note (1) Parameter Input capacitance for user I/O pin ...

Page 104

... These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. 5–14 Cyclone II Device Handbook, Volume 1 consumption and then select CCINT Table 5–14 shows the status of the Altera Corporation February 2008 ...

Page 105

... Table 5–14. Cyclone II Device Timing Model Status Device EP2C5/A EP2C8/A EP2C15A EP2C20/A EP2C35 EP2C50 EP2C70 Performance Table 5–15 performance values were obtained with Quartus II software compilation of LPM, or MegaCore functions for the FIR and FFT designs. ...

Page 106

... Altera Corporation February 2008 ...

Page 107

... Quad Output, 2 Parallel FFT Engines, Buffered Burst, 3 Mults/5 Adders FFT function 8-bit, 1024 pt, Quad Output, 2 Parallel FFT Engines, Buffered Burst, 4 Mults/2 Adders FFT function Altera Corporation February 2008 DC Characteristics and Timing Specifications Resources Used M4K –6 DSP LEs Memory ...

Page 108

... Speed Speed Grade Grade Grade Grade (6) (7) 200.0 195.0 149.23 163.02 200.0 195.0 151.28 163.02 –8 Speed Grade (3) Unit Min Max –40 — ps –40 — ps 306 — ps 306 — ps 135 304 ps 141 — ps 244 — ps 244 — ps Altera Corporation February 2008 ...

Page 109

... Min TSU 76 — — TCO 99 — TPIN2COMBOUT_R 384 — TPIN2COMBOUT_C 385 — TCOMBIN2PIN_R 1344 — Altera Corporation February 2008 DC Characteristics and Timing Specifications (1) –7 Speed Grade (2) Max Min Max — 244 — — 217 — — 1242 — — 1111 — ...

Page 110

... Speed Grade (3) Unit Min Max 62 — — ps 113 — ps 113 — — ps 621 2441 ps 652 — ps 621 2441 ps 652 — ps Altera Corporation February 2008 ...

Page 111

... The second row represents the minimum timing parameter for commercial devices. Table 5–19. M4K Block Internal Timing Microparameters (Part Parameter TM4KRC TM4KWERESU TM4KWEREH TM4KBESU Altera Corporation February 2008 DC Characteristics and Timing Specifications (1) –7 Speed Grade Max Min Max ...

Page 112

... Altera Corporation February 2008 ...

Page 113

... Table 5–21. EP2C5/A Column Pins Global Clock Timing Parameters (Part Fast Corner Parameter Industrial/ Commercial Automotive t 1.283 1.297 –0.188 Altera Corporation February 2008 DC Characteristics and Timing Specifications –6 Speed Grade (1) –7 Speed Grade Min Max Min 191 — 244 — — 217 Tables 5– ...

Page 114

... Speed Grade Unit Grade (2) 0.071 0.081 ns –7 Speed –8 Speed Grade Unit Grade (2) 2.54 2.540 ns 2.548 2.548 ns –0.106 –0.096 ns –0.098 –0.088 ns –7 Speed –8 Speed Grade Unit Grade (2) 2.764 2.774 ns 2.793 2.803 ns 0.016 0.026 ns Altera Corporation February 2008 ...

Page 115

... Fast Corner Parameter Industrial/ Commercial Automotive t 1.621 1.635 –0.351 Altera Corporation February 2008 DC Characteristics and Timing Specifications –7 Speed –6 Speed Grade Grade (1) –0.189 0.089 0.047 –7 Speed –6 Speed Grade Grade (1) 1 ...

Page 116

... Grade Unit Grade (2) 0.075 0.045 ns –7 Speed –8 Speed Grade Unit Grade (2) 2.886 2.866 ns 2.894 2.874 ns –0.077 –0.107 ns –0.069 –0.099 ns –7 Speed –8 Speed Grade Unit Grade (2) 3.009 2.989 ns 3.038 3.018 ns 0.046 0.016 ns Altera Corporation February 2008 ...

Page 117

... Notes to Table 5–28: (1) These numbers are for commercial devices. (2) These numbers are for automotive devices. EP2C35 Clock Timing Parameters Tables 5–29 devices. Table 5–29. EP2C35 Column Pins Global Clock Timing Parameters Fast Corner Parameter Industrial t 1.499 1.513 – ...

Page 118

... Timing Specifications Table 5–30. EP2C35 Row Pins Global Clock Timing Parameters Fast Corner Parameter Industrial t 1.410 1.412 –0.117 –0.115 EP2C50 Clock Timing Parameters Tables 5–31 devices. Table 5–31. EP2C50 Column Pins Global Clock Timing Parameters ...

Page 119

... Clock Network Skew Adders Table 5–35 Table 5–35. Clock Network Specifications Clock skew adder EP2C5/A, EP2C8/A Clock skew adder EP2C15A, EP2C20/A, EP2C35, EP2C50, EP2C70 Note to (1) Altera Corporation February 2008 DC Characteristics and Timing Specifications and 5–34 show the clock timing parameters for EP2C70 – ...

Page 120

... Speed –8 Speed Grade Grade (4) Min Max Min Max Offset Offset Offset Offset 0 4174 0 4290 0 4033 — — Altera Corporation February 2008 Unit Unit ps ps ...

Page 121

... Refer to standards. Table 5–38. Default Loading of Different I/O Standards for Cyclone II Device (Part LVTTL LVCMOS 2.5V 1.8V 1.5V PCI PCI-X SSTL_2_CLASS_I SSTL_2_CLASS_II SSTL_18_CLASS_I Altera Corporation February 2008 DC Characteristics and Timing Specifications Notes –6 Speed Fast Corner (3) Grade Min Max Min Max Offset Offset Offset ...

Page 122

... DIFFERENTIAL_SSTL_2_CLASS_I DIFFERENTIAL_SSTL_2_CLASS_II DIFFERENTIAL_SSTL_18_CLASS_I DIFFERENTIAL_SSTL_18_CLASS_II 1.5V_DIFFERENTIAL_HSTL_CLASS_I 1.5V_DIFFERENTIAL_HSTL_CLASS_II 1.8V_DIFFERENTIAL_HSTL_CLASS_I 1.8V_DIFFERENTIAL_HSTL_CLASS_II LVDS 1.2V_HSTL 1.2V_DIFFERENTIAL_HSTL 5–32 Cyclone II Device Handbook, Volume 1 I/O Standard Capacitive Load Unit Altera Corporation February 2008 ...

Page 123

... I/O Standard LVTTL 2.5V 1.8V 1.5V LVCMOS SSTL_2_CLASS_I SSTL_2_CLASS_II SSTL_18_CLASS_I SSTL_18_CLASS_II Altera Corporation February 2008 DC Characteristics and Timing Specifications Tables 5–39 through 5–43 for I/O delays. Delay from I/O datain to output pad Delay from I/O output register to output pad Delay from input pad to I/O dataout to core Delay from input pad to I/O input register ...

Page 124

... Altera Corporation February 2008 ...

Page 125

... These numbers are for automotive devices. Table 5–41. Cyclone II I/O Input Delay for Row Pins (Part I/O Standard LVTTL 2.5V 1.8V 1.5V LVCMOS SSTL_2_CLASS_I SSTL_2_CLASS_II SSTL_18_CLASS_I SSTL_18_CLASS_II 1.5V_HSTL_CLASS_I Altera Corporation February 2008 DC Characteristics and Timing Specifications Fast Corner Parameter Industrial/ Commer Automotive -cial t 570 597 P I ...

Page 126

... Altera Corporation February 2008 ...

Page 127

... Drive I/O Standard Strength LVTTL (1) LVCMOS (1) Altera Corporation February 2008 DC Characteristics and Timing Specifications Fast Corner Parameter Industrial/ Commer Automotive -cial t 1524 1599 1656 1738 1343 1409 ...

Page 128

... Altera Corporation February 2008 ...

Page 129

... SSTL_18_ 6 mA CLASS_I (1) SSTL_18_ 16 mA CLASS_II 18 mA (1) 1.8V_HSTL_ 8 mA CLASS_I (1) Altera Corporation February 2008 DC Characteristics and Timing Specifications Fast Corner Parameter Industrial/ Commer Automotive -cial t 1196 1254 1328 1393 1174 1231 O P ...

Page 130

... Altera Corporation February 2008 ...

Page 131

... SSTL_18_CLASS_II 18 mA (1) 1.8V_DIFFERENTIAL 8 mA _HSTL_CLASS_I (1) 1.8V_DIFFERENTIAL 16 mA _HSTL_CLASS_II (1) 1.5V_DIFFERENTIAL 8 mA _HSTL_CLASS_I (1) Altera Corporation February 2008 DC Characteristics and Timing Specifications Fast Corner Parameter Industrial/ Commer Automotive -cial t 1472 1544 1604 1683 1469 1541 O P ...

Page 132

... Altera Corporation February 2008 ...

Page 133

... ( 2. ( Altera Corporation February 2008 DC Characteristics and Timing Specifications Fast Corner –6 Industrial Speed Commer- /Auto- Grade cial motive 1343 1408 2539 1467 1540 2747 1198 ...

Page 134

... Altera Corporation February 2008 ...

Page 135

... ( 1.5V_ (1) DIFFERENTIAL_ HSTL_ CLASS_I Altera Corporation February 2008 DC Characteristics and Timing Specifications Fast Corner –6 Industrial Speed Commer- /Auto- Grade cial motive 1364 1430 2853 1488 1562 3061 1332 ...

Page 136

... Table 5–45 Altera Corporation February 2008 Unit ...

Page 137

... PCI PCI-X DIFFERENTIAL_SSTL_2_ CLASS_I DIFFERENTIAL_SSTL_2_ CLASS_II Altera Corporation February 2008 DC Characteristics and Timing Specifications = 1000 / (1000/toggle rate at default load + derating factor * load value in pF/1000) 1000 / (1000/270 + 29 × 10/1000) = 250 (MHz) through 5–46 show the I/O toggle rates for Cyclone II ...

Page 138

... Dedicated Clock (1) Outputs –7 –8 –6 –7 –8 Speed Speed Speed Speed Grade Grade Grade Grade 80 120 100 80 140 200 170 140 190 280 230 190 200 290 240 200 230 330 280 230 250 360 300 250 Altera Corporation February 2008 ...

Page 139

... SSTL_2_CLASS_I SSTL_2_CLASS_II SSTL_18_ 6 mA CLASS_I Altera Corporation February 2008 DC Characteristics and Timing Specifications Maximum Output Clock Toggle Rate on Cyclone II Devices (MHz) Column I/O Pins (1) Row I/O Pins –6 –7 –8 –6 Speed Speed Speed ...

Page 140

... Altera Corporation February 2008 ...

Page 141

... OHMS SSTL_2_CLASS_I OCT_50_ OHMS SSTL_18_CLASS_I OCT_50_ OHMS Note to Table 5–45: (1) This is based on single data rate I/Os. Altera Corporation February 2008 DC Characteristics and Timing Specifications Maximum Output Clock Toggle Rate on Cyclone II Devices (MHz) Column I/O Pins (1) Row I/O Pins –6 –7 –8 –6 Speed Speed ...

Page 142

... Altera Corporation February 2008 ...

Page 143

... DIFFERENTIAL_SSTL_2 16 mA _CLASS_II DIFFERENTIAL_SSTL_ 6 mA 18_CLASS_I Altera Corporation February 2008 DC Characteristics and Timing Specifications Maximum Output Clock Toggle Rate Derating Factors (ps/pF) Column I/O Pins Row I/O Pins –6 –7 –8 –6 Speed Speed Speed Speed ...

Page 144

... Altera Corporation February 2008 ...

Page 145

... High-speed I/O data rate HSIODR High-speed receiver and transmitter input and output data rate. Time unit interval TUI Channel-to-channel skew TCCS Altera Corporation February 2008 DC Characteristics and Timing Specifications Maximum Output Clock Toggle Rate Derating Factors (ps/pF) Column I/O Pins Row I/O Pins –6 – ...

Page 146

... Peak-to-peak output jitter on high-speed PLLs. Low-to-high transmission time. High-to-low transmission time. Lock time for high-speed transmitter and receiver PLLs. Time Unit Interval (TUI) RSKM Sampling Window (SW) shows the high-speed I/O timing budget expected to be centered SU H RSKM TCCS Altera Corporation February 2008 ...

Page 147

... Mbps ×7 70 ×4 40 ×2 20 × — Altera Corporation February 2008 DC Characteristics and Timing Specifications Note (1) RSKM SW shows the RSDS timing budget for Cyclone II devices at –7 Speed Grade Typ Max(1) Min Typ Max(1) — 155.5 10 — ...

Page 148

... Therefore, the transmitter timing parameter H (minimum) and t CO –8 Speed Grade Unit Min Typ Max(1) — — 200 ps — — 500 ps — 500 — ps — 500 — ps μs — — 100 High-Speed Differential (maximum). Refer to Figure 5–4 CO Figure 5–5. Altera Corporation February 2008 ...

Page 149

... Conditions Min f × (input ×8 10 clock ×7 10 frequency) ×4 10 ×2 10 ×1 10 Altera Corporation February 2008 DC Characteristics and Timing Specifications Transmitter Clock (5.88 ns) Transmitter Transmitter Valid Data Valid Data Total Skew ns) H shows the mini-LVDS transmitter timing budget for Cyclone II – ...

Page 150

... Mbps 70 — 311 Mbps 40 — 311 Mbps 20 — 311 Mbps 10 — 311 Mbps 45 — — — 200 ps — — 500 ps — — 500 ps — — 500 ps μs — — 100 (minimum) and t (maximum). CO Figure 5–6. t (2) H Altera Corporation February 2008 ...

Page 151

... Output — — — jitter (peak to peak) t 20–80% 150 200 Altera Corporation February 2008 DC Characteristics and Timing Specifications and 5–51 show the LVDS timing budget for Cyclone II –7 Speed Grade Max Max Max Min Typ (1) (2) (1) — ...

Page 152

... –8 Speed Grade Max Max Max Min Typ (2) (1) (2) 150 200 250 (11) — — (12) 100 of 250 ps, the Altera Corporation February 2008 Unit ps μs ...

Page 153

... For extended temperature devices, the maximum data rate for x1 mode is 340 Mbps. (5) For extended temperature devices, the maximum lock time is 500 us. External Memory Interface Specifications Table 5–52 Table 5–52. DQS Bus Clock Skew Adder Specifications Note to (1) Altera Corporation February 2008 DC Characteristics and Timing Specifications –7 Speed Grade Typ Max Min Typ Max — ...

Page 154

... Cyclone II Device Handbook, Volume 1 shows the timing requirements for the JTAG signals. TMS TDI t JCP t t JCH JCL TCK t t JPZX JPCO TDO t t JSSU JSH JSCO JSZX JPSU JPH t JPXZ t JSXZ Altera Corporation February 2008 ...

Page 155

... LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time and port clock to output time For more information on JTAG, refer to the Boundary-Scan Testing for Cyclone II Devices Handbook. Altera Corporation February 2008 DC Characteristics and Timing Specifications shows the JTAG timing parameters and values for Cyclone II Min (2) (2) ...

Page 156

... MHz 40 — — 200 — ps (4) 10 — MHz (4) 10 — MHz 10 — (4) MHz 10 — 500 MHz 10 — 450 MHz 10 — 402.5 MHz 45 — — — 300 ps — — 30 mUI μs — — 100 (6) — — ±60 ps Altera Corporation February 2008 ...

Page 157

... DCD for a clock is the larger value of D1 and D2. Figure 5–8. Duty Cycle Distortion DCD expressed in absolution derivation, for example Figure percentage, and the percentage number is clock-period dependent. DCD as a percentage is defined as: Altera Corporation February 2008 DC Characteristics and Timing Specifications Note (1) (Part Parameter areset signal ...

Page 158

... DCD. 5–68 Cyclone II Device Handbook, Volume 1 (T/2 – D1 (the low percentage boundary) (T (the high percentage boundary) DFF D Q (Figure 5–10). Therefore, any distortion on the input (Figure 5–9). Therefore, any DCD output Altera Corporation February 2008 ...

Page 159

... DCD as a percentage. Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O Pins LVCMOS LVTTL 2.5-V 1.8-V 1.5-V SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I HSTL-15 Class I HSTL-18 Class I Altera Corporation February 2008 DC Characteristics and Timing Specifications DFF PRN D Q GND CLRN V DFF CC PRN ...

Page 160

... Unit 165 165 85 155 155 145 145 205 195 255 255 195 255 255 Notes (1), ( Unit 195 285 285 210 305 305 Altera Corporation February 2008 ...

Page 161

... Table 5–57. Maximum for DDIO Output on Row Pins with PLL in the Clock Path Row Pins with PLL in the Clock Path LVCMOS LVTTL 2.5-V 1.8-V Altera Corporation February 2008 DC Characteristics and Timing Specifications Column I/O Output Standard Table 5–56: The DCD specification is characterized using the maximum drive strength available for each I/O standard ...

Page 162

... Table 5–57). If the clock Altera Corporation February 2008 ...

Page 163

... Differential HSTL-18 Class I Differential HSTL-18 Class II Differential HSTL-15 Class I Differential HSTL-15 Class II LVDS Simple RSDS Mini-LVDS Notes to (1) (2) Altera Corporation February 2008 DC Characteristics and Timing Specifications Notes (1), (2) Table 5–58: The DCD specification is characterized using the maximum drive strength available for each I/O standard. ...

Page 164

... PowerPlay Power Analysis chapters in volume 3 of the Quartus II Handbook shows the revision history for this document. Changes Made Documents”. 5–3. chapter of the Summary of Changes Added I/O timing numbers for automotive-grade devices. Updated R typical and maximum CONF values in Table 5–3. Altera Corporation February 2008 ...

Page 165

... November 2004 Updated the “Differential I/O Standards” v1.1 Updated Table 5–54. June 2004 Added document to the Cyclone II Device Handbook. v1.0 Altera Corporation February 2008 DC Characteristics and Timing Specifications minimum and maximum limitations in in Table 5–2. rise time for Cyclone II CC Table 5–2. information in Table 5– ...

Page 166

... Document Revision History 5–76 Cyclone II Device Handbook, Volume 1 Altera Corporation February 2008 ...

Page 167

... Device pin-outs for Cyclone II devices are available on the Altera web site (www.altera.com). For more information contact Altera Applications. Ordering Figure 6–1 information on a specific package, contact Altera Applications. Information Altera Corporation February 2007 6. Reference & Ordering ® II devices are supported by the Altera ® ...

Page 168

... Speed Grade with 6 being the fastest Operating Temperature ° ° C: Commercial temperature ( ° ° I: Industrial temperature ( 100 C) J Summary of Changes ● Added Ultra FineLine BGA detail in UBGA Package information in Figure 6–1. Altera Corporation February 2007 ...