epf6016ati144-2 Altera Corporation, epf6016ati144-2 Datasheet
epf6016ati144-2
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epf6016ati144-2 Summary of contents
Page 1
... Supply voltage (V ) 3.3 V CCINT Note: (1) The embedded IEEE Std. 1149.1 JTAG circuitry adds up to 14,000 gates in addition to the listed typical gates. Altera Corporation A-DS-F6000-04.1 ® Register-rich, look-up table- (LUT-) based architecture ® OptiFLEX architecture that increases device area efficiency Typical gates ranging from 5,000 to 24,000 gates (see Built-in low-skew clock distribution tree 100% functional testing of all devices ...
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... Footprint- and pin-compatibility with other FLEX 6000 devices in the same package 144-Pin 208-Pin 240-Pin TQFP PQFP PQFP 102 117 171 199 117 171 117 171 199 Table 2) ® 6000 devices) Table 2) 256-Pin 256-pin BGA FineLine BGA 204 171 218 219 Altera Corporation ...
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... Note: (1) This performance value is measured as a pin-to-pin delay. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet ® FLEX 6000 programmable logic device (PLD) family provides shows FLEX 6000 performance for some common designs. All ...
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... Grade 599 94 1,182 75 63 487 36 609 56 TM functions MAX+PLUS II Programmable Logic Development System & Software and the Quartus Programmable Logic Development System & for more information. Units -3 Speed Grade 80 72 MSPS µS 89 109 53 43 MHz 30 25 MHz 49 42 MHz . Altera Corporation ...
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... The LABs are interconnected by the FastTrack Interconnect. IOEs are located at the end of each FastTrack Interconnect row and column. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet shows a block diagram of the FLEX 6000 OptiFLEX architecture. ...
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... FLEX 6000 architecture, and facilitates efficient routing with optimum device utilization and high performance. 6 IOEs Row FastTrack Interconnect Row FastTrack Interconnect Column FastTrack Interconnect Local Interconnect (Each LAB accesses two local interconnect areas.) Logic Elements Altera Corporation ...
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... In addition, counters may also have synchronous clear or load signals design that uses non-global clock and clear signals, inputs from the first LAB are re-routed to drive the control signals for that LAB. See Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Figure 2. ...
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... An LE contains a programmable flipflop, carry and cascade chains. Additionally, each LE drives both the local and the FastTrack Interconnect. See LABCTRL1/ LABCTRL2 SYNCLR CLK1/SYNLOAD CLK2 LAB-wide control signals (SYNCLR and SYNLOAD signals are used in counter mode). Figure 4. Altera Corporation ...
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... LAB and all LABs in the same half of the row. Because extensive use of carry and cascade chains can reduce routing flexibility, these chains should be limited to speed-critical portions of a design. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Register Bypass Carry-In ...
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... The final carry-out signal is routed to an LE, where it is driven onto the FastTrack Interconnect. 10 shows how an n-bit full adder can be implemented LEs Altera Corporation ...
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... Figure 5. Carry Chain Operation Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Carry-In LUT Carry Chain LUT Carry Chain LUT Carry Chain LUT Carry Chain s1 Register LE 2 Register Register Register Carry-Out ...
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... LAB. Figure 6 functions with a wide fan-in. In this example, functions of 4n variables are implemented with n LEs. The cascade chain requires 3 decode a 16-bit address. 12 shows how the cascade function can connect adjacent LEs to form Altera Corporation ...
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... If required, the designer can also create special-purpose functions to use an LE operating mode for optimal performance. Figure 7 Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet OR Cascade Chain LE 2 d[3.. d[7 ...
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... LEs other than the second LAB. (3) The LAB-wide synchronous clear and LAB-wide synchronous load affect all registers in an LAB. 14 Cascade-In PRN D CLRN Cascade-Out Cascade-In PRN D Q CLRN Cascade-Out LAB-Wide Synchronous LAB-Wide Synchronous (3) (3) Load Clear Cascade-In PRN D CLRN Carry-Out Cascade-Out LE-Out Q LE-Out LE-Out Q Altera Corporation ...
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... If the cascade function is used counter mode, the synchronous clear or load will override any signal carried on the cascade chain. The synchronous clear overrides the synchronous load. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet 7, the first LUT uses the carry-in signal and two data inputs from ...
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... Because the clear and preset functions are active-low, the Altera software automatically assigns a logic high to an unused clear or preset signal. The clear and preset logic is implemented in either the asynchronous clear or asynchronous preset mode, which is chosen during design entry (see 16 Figure 8). Altera Corporation ...
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... This global routing structure provides predictable performance, even for complex designs. In contrast, the segmented routing in FPGAs requires switch matrices to connect a variable number of routing paths, increasing the delays between logic resources and reducing performance. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Asynchronous Preset Chip-Wide Reset ...
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... For EPF6010A, EPF6016, and EPF6016A devices 144 channels and channels; for EPF6024A devices 186 channels and channels Column Interconnect (m Channels) (1) Figure 9 shows through To/From Adjacent 5 LAB through LE 10 Altera Corporation ...
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... LABs LEs, via the local interconnect. The row-to-local multiplexers are used more efficiently, because the multiplexers can now drive two LABs. column interconnects. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Figure 10 shows how an LAB connects to row and ...
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... FastTrack Interconnect can channels. drive two column channels Column Interconnect Any column channel can drive six row channels can be driven by any signal from two local interconnect areas. Row Interconnect From Adjacent Local Interconnect Altera Corporation ...
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... FastTrack Interconnect and do not receive any advantage from being routed on global signals. This LE-driving-global control signal feature is controlled by the designer and is not used automatically by the Altera software. See Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet summarizes the FastTrack Interconnect resources available in Rows ...
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... Global signals drive into every LAB as clock, asynchronous clear, preset, and data signals. (4) The local interconnect from LABs C22 and D22 can drive two global control signals on the right side. 22 Note (1) 4 (3) (4) LAB (Repeated LAB C22 Across Device) (4) LAB D22 Dedicated Inputs Altera Corporation ...
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... A chip-wide output enable feature allows the designer to disable all pins of the device by asserting one pin (DEV_OE). This feature is useful during board debugging or testing. Figure 12 Figure 12. IOE Block Diagram Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet shows the IOE block diagram. To Row or Column Interconnect Chip-Wide Output Enable ...
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... Each IOE can drive up to six row LAB channels, and each IOE data and OE signal is driven by IOE the local interconnect. FastFLEX I/ can drive a pin through the local interconnect for faster clock-to-output times. shows how an Altera Corporation ...
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... SameFrame pin-out devices. Devices can be defined for present and future use. The Altera software packages generate pin-outs describing how to lay out a board to take advantage of this migration (see Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Each IOE can drive two column interconnect channels ...
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... Designed for 256-Pin FineLine BGA Package 100-Pin FineLine BGA 256-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements) lists the 3.3-V FLEX 6000 devices with the SameFrame pin-out Device 100-Pin FineLine BGA v 256-Pin FineLine BGA (Increased I/O Count or Logic Requirements) 256-Pin FineLine BGA v v Altera Corporation ...
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... MultiVolt I/Os are not supported on 100-pin TQFP or 100-pin FineLine BGA packages. Table 7 Table 7. FLEX 6000 MultiVolt I/O Support V CCINT (V) 3.3 3.3 5.0 5.0 Note: (1) When V tolerant inputs. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet CCINT . OD1 describes FLEX 6000 MultiVolt I/O support. V Input Signal (V) CCIO (V) 2.5 3.3 5 ...
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... V. When the open-drain pin is active, it will drive low. IH current specification should be considered when OL and V CCIO CCINT Table 8 See Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices) for more information on JTAG BST circuitry. Description = 3 5.0 V (with CCIO power planes can be powered shows JTAG instructions for Altera Corporation ...
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... Figure 16. JTAG Waveforms TMS TDI TCK TDO Signal to Be Captured Signal to Be Driven Table 10 devices. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Device EPF6010A EPF6016 EPF6016A EPF6024A for more information. shows the timing requirements for the JTAG signals. t JCP t t ...
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... Min Max Unit 100 Figure 17. Multiple VCC 464 Ω (703 Ω) [521 Ω] To Test System 250 Ω C1 (includes [481 Ω] JIG capacitance) Altera Corporation ...
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... Output voltage O T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet through 18 provide information on absolute maximum ratings, Note (1) Conditions With respect to ground (2) No bias Under bias PQFP, TQFP, and BGA packages ...
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... 1.0 MHz 1.0 MHz 1.0 MHz OUT Sheet. must rise monotonically 5 Min Typ Max Unit 2 0.5 V CCINT –0.5 0.8 V 2.4 V 2.4 V – 0.2 V CCIO 0.45 V 0.45 V 0.2 V –10 10 µA –40 40 µA 0 Min Max Unit Table 12 on Altera Corporation ...
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... Input voltage I V Output voltage O T Operating temperature J t Input rise time R t Input fall time F Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Note (1) Conditions ground With respect to (2) No bias Under bias PQFP, PLCC, and BGA packages Conditions (3), (4) 3.00 (3.00) ...
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... 1.0 MHz 1.0 MHz 1.0 MHz OUT Sheet. must rise monotonically 3 33. (6) Min Typ Max Unit 1.7 5.75 V –0.5 0.8 V 2.4 V – 0.2 V CCIO 2.1 V 2.0 V 1.7 V 0.45 V 0.2 V 0.2 V 0.4 V 0.7 V –10 10 µA –10 10 µA 0 Min Max Unit Altera Corporation ...
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... CCI NT V CCI O Room Temperature 75 Typical I O Output Current (mA Output Voltage (V) O Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet shows the typical output drive characteristics of 5.0-V and 3.3-V EPF6010A EPF6016A = 3.3 V 100 = 3 Typical Output Current (mA) 50 ...
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... The Timing Analyzer provides point-to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Figure 19 routing paths to and from the various elements of the FLEX 6000 device ROW + LOCAL ) DATA_TO_REG ) SU shows the overall timing model, which maps the possible t ) REG_TO_OUT Altera Corporation ...
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... LOCAL CARRY_TO_REG t DATA_TO_REG LD_CLR t CARRY_TO_CARRY t REG_TO_CARRY t DATA_TO_CARRY t t LABCARRY DIN_D t DIN_C Carry-out to Next LE in Same LAB Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet t ROW Cascade-In from Previous LE t CASC_TO_OUT t CARRY_TO_OUT t DATA_TO_OUT t t REG_TO_OUT CLR t ...
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... Cascade-in to cascade-out delay CASC_TO_CASC t Register-out to cascade-out delay REG_TO_CASC t LE input to cascade-out delay DATA_TO_CASC t LE register clock high time register clock low time CL 38 through 21 describe the FLEX 6000 internal timing Tables 22 and 23 describe FLEX 6000 external timing Note (1) Parameter Conditions Altera Corporation ...
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... different LAB Table 22. External Reference Timing Parameters Symbol t Register-to-register test pattern 1 t Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local DRR interconnects Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Note (1) Parameter = V CCIO CCINT = low voltage CCIO = V ...
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... Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part Parameter -1 Min Max t REG_TO_REG t CASC_TO_REG t CARRY_TO_REG t DATA_TO_REG t CASC_TO_OUT t CARRY_TO_OUT t DATA_TO_OUT t REG_TO_OUT Parameter through 28 show the timing information for EPF6010A and Speed Grade -2 Min Max 1.2 1.3 0.9 1.0 0.9 1.0 1.1 1.2 1.3 1.4 1.6 1.8 1.7 2.0 0.4 0.4 1.0 1.7 Conditions (8) (8) (8) Unit -3 Min Max 1.7 ns 1.2 ns 1.2 ns 1.5 ns 1.8 ns 2.3 ns 2.5 ns 0.5 ns 1.3 ns 2.1 ns Altera Corporation ...
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... DATA_TO_CASC t 2 2.5 CL Table 25. IOE Timing Microparameters for EPF6010A & EPF6016A Devices Parameter -1 Min Max t OD1 t OD2 t OD3 XZ1 t XZ2 t XZ3 t IOE IN_DELAY Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Speed Grade -2 Min Max 0.3 0.4 0.4 0.4 1.8 2.1 1.8 2.1 0.1 0.1 1.6 1.9 2.1 2.5 1.0 1.1 0.5 0.6 1.4 1.7 1.1 1.2 3.0 3.0 Speed Grade -2 ...
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... Hold time is zero when the Increase Input Delay option is turned on. 42 Speed Grade -2 Min Max 0.7 0.7 2.9 3.2 1.2 1.3 5.4 5.7 4.3 5.0 2.6 3.0 0.7 0.8 1.3 1.4 Speed Grade -1 -2 Max Min Max 37.6 43.6 38.0 44.0 Speed Grade -2 Min Max 2.4 (1) 0.3 (2) 7.1 2.0 8.2 Unit -3 Min Max 1.0 ns 3.2 ns 1.4 ns 6.4 ns 6.1 ns 3.7 ns 0.9 ns 1.8 ns Unit -3 Min Max 53.7 ns 54.1 ns Unit -3 Min Max 3.3 (1) ns 0.1 (2) ns 2.0 10.1 ns Altera Corporation ...
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... DATA_TO_CARRY t CARRY_TO_CASC t CASC_TO_CASC t REG_TO_CASC t DATA_TO_CASC t 4 4.0 CL Table 30. IOE Timing Microparameters for EPF6016 Devices Parameter Min t OD1 t OD2 Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet through 33 show the timing information for EPF6016 devices. Speed Grade -2 -3 Max Min 2.2 0.9 1.6 2.4 1.3 2.4 2.7 0.3 1.6 2.3 0.3 0.5 1 ...
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... Table 32. External Reference Timing Parameters for EPF6016 Devices Parameter Min DRR 44 Speed Grade -2 -3 Max Min 4.7 2.3 2.3 4.6 4.7 0.5 3.3 4.6 Speed Grade -2 -3 Max Min 0.8 2.9 2.3 4.9 4.8 3.1 0.4 0.8 Speed Grade -2 -3 Max Min 53.0 16.0 Unit Max 5.2 ns 2.8 ns 2.8 ns 5.1 ns 5.2 ns 0.6 ns 4.0 ns 5.6 ns Unit Max 1.0 ns 3.3 ns 2.5 ns 6.0 ns 6.0 ns 3.9 ns 0.5 ns 1.0 ns Unit Max 65.0 ns 20.0 ns Altera Corporation ...
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... CLR LD_CLR t CARRY_TO_CARRY t REG_TO_CARRY t DATA_TO_CARRY t CARRY_TO_CASC t CASC_TO_CASC t REG_TO_CASC t DATA_TO_CASC t 2 2.5 CL Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Speed Grade -2 Max Min 4.1 0.0 7.9 2.0 through 38 show the timing information for EPF6024A devices. Speed Grade -2 Min Max 1.2 1.3 0.7 0.8 1.6 1.8 1.3 1.4 1.2 1.3 2.0 2.2 1.8 2.1 0.3 ...
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... Table 37. External Reference Timing Parameters for EPF6024A Devices Parameter -1 Min Max t 45 Speed Grade -2 Min Max 1.9 2.1 4.0 4.4 7.0 7.8 4.3 4.8 4.3 4.8 6.4 7.1 9.4 10.5 0.5 0.6 3.3 3.7 5.3 5.9 Speed Grade -2 Min Max 0.8 0.8 3.0 3.1 3.0 3.2 5.4 5.6 4.6 5.1 3.1 3.5 0.6 0.7 0.3 0.3 Speed Grade -2 Min Max 50.0 Unit -3 Min Max 2.5 ns 5.3 ns 9.3 ns 5.8 ns 5.8 ns 8.6 ns 12.6 ns 0.7 ns 4.4 ns 7.0 ns Unit -3 Min Max 1.1 ns 3.3 ns 3.4 ns 6.2 ns 6.1 ns 4.3 ns 0.8 ns 0.4 ns Unit -3 Min Max 60.0 ns Altera Corporation ...
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... This value is based on the amount of current that each LE typically consumes. The P characteristics and switching frequency, can be calculated using the guidelines given in The I CCACTIVE I CCACTIVE Where: f MAX N tog LC K Table 39. K Constant Values Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet Speed Grade -2 Min Max 2.2 (1) 0.2 (2) 7.4 2.0 8 × V ...
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... FPGA. Figure 20 frequency for EPF6010A, EPF6016, EPF6016A, and EPF6024A devices. 48 estimate based on typical conditions with CC should be verified during operation CC shows the relationship between the current and operating Altera Corporation ...
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... Operation f See Application Note 116 (Configuring APEX 20K, FLEX 10K & FLEX 6000 Devices) including sample schematics, timing diagrams, configuration options, pins names, and timing parameters. Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet EPF6016 1000 800 I Supply CC ...
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... Configuration device Passive serial (PS) Passive serial asynchronous (PSA) 50 shows the data sources for each configuration scheme. Data Source EPC1 or EPC1441 configuration device TM BitBlaster , ByteBlasterMV download cables, or serial data source BitBlaster, ByteBlasterMV, or MasterBlaster download cables, or serial data source MasterBlaster Altera Corporation ...
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... Device Pin- See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. Outs Altera Corporation FLEX 6000 Programmable Logic Device Family Data Sheet 51 ...
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... Altera, BitBlaster, ByteBlasterMV, FastFlex, FastTrack, FineLine BGA, FLEX, MasterBlaster, MAX+PLUS II, MegaCore, MultiVolt, OptiFLEX, Quartus, SameFrame, and specific device designations are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog is a registered trademark of and Verilog- trademarks of Cadence Design Systems, Inc ...