epf10k50sqi208-2 Altera Corporation, epf10k50sqi208-2 Datasheet

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... Feature Typical gates (1) Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Altera Corporation DS-F10KE-2.5 ® Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – ...

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... Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – Clamp to V user-selectable on a pin-by-pin basis CCIO – Supports hot-socketing EPF10K130E EPF10K200E EPF10K200S 130,000 200,000 342,000 513,000 6,656 9,984 16 24 65,536 98,304 413 470 TM options for reduced clock Altera Corporation ...

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... FineLine BGA packages are pin-compatible. For example, a board can be designed to support 256-pin, 484-pin, and 672-pin FineLine BGA packages. The Altera software automatically avoids conflicting pins when future migration is set. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Software design support and automatic place-and-route provided by Altera’ ...

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... RQFP BGA 0.50 1.0 1,197 289 1,225 30.6 34.6 34 shows FLEX 10KE performance for some common designs. All 356- 484-Pin 599-Pin Pin FineLine PGA BGA BGA 1.27 1.0 – 529 3,904 23 62.5 62 Altera Corporation 600- 672-Pin Pin FineLine BGA BGA 1.27 1.0 2,025 729 27 testing prior ...

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... Note: (1) These values are for calculation time. Calculation time = number of clocks required/f required = ceiling [log 2 (points)/2] Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Resources Used LEs EABs -1 Speed Grade -2 Speed Grade -3 Speed Grade 16 ...

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... FLEX 10KE devices contain an interface that permits microprocessors to configure FLEX 10KE devices serially or in-parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat a FLEX 10KE device as memory and configure it by writing to a virtual memory location, making it easy to reconfigure the device ByteBlasterMV MasterBlaster download cables. Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet For more information on FLEX device configuration, see the following documents: Configuration Devices for APEX & FLEX Devices Data Sheet BitBlaster Serial Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet MasterBlaster Download Cable Data Sheet Application Note 116 (Configuring APEX 20K, FLEX 10K, & ...

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... When used with a dedicated clock pin, these registers provide exceptional performance. As inputs, they provide setup times as low as 0.9 ns and hold times of 0 ns. As outputs, these registers provide clock-to-output times as low as 3.0 ns. IOEs provide a variety of features, such as JTAG BST support, slew-rate control, tri-state buffers, and open-drain outputs. 8 Altera Corporation ...

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... Interconnect Logic Array IOE IOE Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 1 shows a block diagram of the FLEX 10KE architecture. Each group of LEs is combined into an LAB; groups of LABs are arranged into rows and columns. Each row also contains a single EAB. The LABs and EABs are interconnected by the FastTrack Interconnect routing structure ...

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... When in dual-port mode, separate clocks may be used for EAB read and write sections, which allows the EAB to be written and read at different rates. It also has separate synchronous clock enable signals for the EAB read and write sections, which allow independent control of these sections. 10 Altera Corporation ...

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... EPF10K30E and EPF10K50E devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, and EPF10K200E devices have 104 EAB local interconnect channels. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet The EAB can also be used for bidirectional, dual-port memory applications where two ports read or write simultaneously. To implement this type of dual-port memory, two EABs are used to support two simultaneous read or writes ...

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... Figure 3. FLEX 10KE EAB in Dual-Port RAM Mode The FLEX 10KE EAB can be used in a single-port mode, which is useful for backward-compatibility with FLEX 10K designs (see 12 Port A address_a[] data_a[] we_a clkena_a Clock A Figure Port B address_b[] data_b[] we_b clkena_b Clock B Figure 4). Altera Corporation 3. ...

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... EAB Local Interconnect (1) Note: (1) EPF10K30E, EPF10K50E, and EPF10K50S devices have 88 EAB local interconnect channels; EPF10K100E, EPF10K130E, EPF10K200E, and EPF10K200S devices have 104 EAB local interconnect channels. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Chip-Wide Row Interconnect Reset ...

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... EABs can be cascaded to form RAM blocks 2,048 words without impacting timing. The Altera software automatically combines EABs to meet a designer’s RAM specifications. 14 256 16 512 8 Figure 6). 256 32 256 16 256 16 2 (see Figure 5). 2,048 2 1,024 4 16 block 512 16 512 8 512 8 Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet EABs provide flexible options for driving and controlling clock signals. Different clocks and clock enables can be used for reading and writing to the EAB. Registers can be independently inserted on the data input, EAB output, write address, write enable signals, read address, and read enable signals ...

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... Row Interconnect 6 4 Carry-In & Cascade- LE1 4 LE2 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 terconnect ter Carry-Out & Cascade-Out See Figure 12 for details. Column-to-Row Interconnect terconnect ter Column Interconnect ter terconnect Altera Corporation ...

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... Chip-Wide Reset labctrl3 labctrl4 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks, the other two can be used for clear/preset control. The LAB clocks can be driven by the dedicated clock input pins, global signals, I/O signals, or internal signals via the LAB local interconnect ...

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... LAB in a row carries to the first LE of the third LAB in the row. The carry chain does not cross the EAB at the middle of the row. For instance, in the EPF10K50E device, the carry chain stops at the eighteenth LAB and a new one begins at the nineteenth LAB. 18 Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 9 shows how an n-bit full adder can be implemented LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE ...

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... Figure 10. FLEX 10KE Cascade Chain Operation AND Cascade Chain d[3..0] LUT d[7..4] LUT d[(4n – 1)..(4n – 4)] LUT 20 shows how the cascade function can connect adjacent LEs to OR Cascade Chain d[3..0] LE1 d[7..4] LE2 d[(4n – 1)..(4n – 4)] LEn LUT LE1 LUT LE2 LUT LEn Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet LE Operating Modes The FLEX 10KE LE can operate in the following four modes: Normal mode Arithmetic mode Up/down counter mode Clearable counter mode Each of these modes uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE— ...

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... Carry-Out Cascade-In 3-Input 1 LUT 0 3-Input LUT Carry-Out 3-Input 1 LUT 0 3-Input LUT Carry-Out LE-Out to FastTrack Interconnect PRN D Q LE-Out to Local ENA Interconnect CLRN LE-Out PRN D Q ENA CLRN PRN D Q ENA CLRN Cascade-Out PRN D Q ENA CLRN Cascade-Out LE-Out LE-Out Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Normal Mode The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT ...

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... Compiler automatically assigns a logic high to an unused clear or preset. The clear and preset logic is implemented in one of the following six modes chosen during design entry: 24 Asynchronous clear Asynchronous preset Asynchronous clear and preset Asynchronous load with clear Asynchronous load with preset Asynchronous load without clear or preset Altera Corporation ...

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... NOT Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet In addition to the six clear and preset modes, FLEX 10KE devices provide a chip-wide reset pin that can reset all registers in the device. Use of this feature is set during design entry. In any of the clear and preset modes, the chip-wide reset overrides all other signals ...

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... LABCTRL1 loads the register. The Altera software inverts the signal that drives DATA3 to account for the inversion of the register’s output. Asynchronous Load without Preset or Clear When implementing an asynchronous load without preset or clear, LABCTRL1 implements the asynchronous load of DATA3 by controlling the register preset and clear. 26 Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet FastTrack Interconnect Routing Structure In the FLEX 10KE architecture, connections between LEs, EABs, and device I/O pins are provided by the FastTrack Interconnect routing structure, which is a series of continuous horizontal and vertical routing channels that traverses the device. This global routing structure provides predictable performance, even in complex designs ...

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... each intersection, six row channels can drive column channels. Each LE can switch interconnect access with the adjacent LAB. To LAB Local Interconnect Column Channels To Other Columns From Adjacent LAB To Adjacent LAB To Other Rows Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet For improved routing, the row interconnect consists of a combination of full-length and half-length channels. The full-length channels connect to all LABs in a row; the half-length channels connect to the LABs in half of the row. The EAB can be driven by the half-length channels in the left half of the row and by the full-length channels ...

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... IOE LAB LAB A2 A3 LAB LAB B2 B3 IOE IOE IOE IOE See Figure 17 for details. IOE IOE LAB A5 LAB A4 Cascade & Carry Chains LAB B5 LAB B4 IOE IOE Figure 15 shows the bidirectional I/O Altera Corporation IOE IOE See Figure 16 for details. IOE IOE ...

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... Peripheral 4 Dedicated Control Bus Inputs 2 4 Note: (1) All FLEX 10KE devices (except the EPF10K50E and EPF10K200E devices) have a programmable input delay buffer on the input path. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet 12 VCC Chip-Wide VCC OE[7..0] (1) Programmable Delay VCC CLK[1 ...

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... When the true and complement of a dedicated input drives IOE clocks, two signals on the peripheral control bus are consumed, one for each sense of the clock eight output enable signals Up to six clock enable signals Up to two clock signals Up to two clear signals Altera Corporation ...

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... OE5 CLKENA0/CLK0/GLOBAL0 CLKENA1/OE6/GLOBAL1 CLKENA2/CLR0 CLKENA3/OE7/GLOBAL2 CLKENA4/CLR1 CLKENA5/CLK1/GLOBAL3 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet When dedicated inputs drive non-inverted and inverted peripheral clears, clock enables, and output enables, two signals on the peripheral control bus will be used. Tables 8 and ...

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... Row E Row E Row G Row L Row N Row I Row K Row K Row M Row F Row H Row D Row F Row B Row D Row H Row J Row J Row L Row G Row I EPF10K200E EPF10K200S Row G Row I Row K Row R Row O Row Q Row L Row J Row H Row N Row P Row M Tables 8 and 9. An internally Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Row-to-IOE Connections When an IOE is used as an input signal, it can drive two separate row channels. The signal is accessible by all LEs within that row. When an IOE is used as an output, the signal is driven by a multiplexer that selects a signal from the row channels ...

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... FLEX 10KE column-to-IOE interconnect resources. Table 11. FLEX 10KE Column-to-IOE Interconnect Resources Device Channels per Column (n) Column Channels per Pin (m) EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K130E EPF10K200E EPF10K200S Table 11. Each IOE is driven by a m-to-1 multiplexer IOE1 m IOE1 Altera Corporation ...

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... SameFrame Pin-Outs Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet FLEX 10KE devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. ...

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... GCLK1 pin. In the Altera software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the FLEX 10KE device. However, when both circuits are used, the other clock pin cannot be used. 38 Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet ClockLock & ClockBoost Timing Parameters For the ClockLock and ClockBoost circuitry to function properly, the incoming clock must meet certain requirements. If these specifications are not met, the circuitry may not lock onto the incoming clock, which generates an erroneous clock within the device ...

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... Duty cycle for ClockLock or OUTDUTY ClockBoost-generated clock 40 and 13 summarize the ClockLock and ClockBoost parameters Condition (3) t < 100 INCLKSTB t < 50 INCLKSTB Min Typ Max 180 16 90 (2) 25,000 100 10 250 (4) 200 Altera Corporation Unit MHz MHz PPM ps µ ...

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... The t specification is measured under long-term observation. The maximum value for t JITTER t is lower than 50 ps. INCLKSTB I/O Configuration Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Condition (3) t < 100 INCLKSTB t < 50 INCLKSTB value is less than the time required for configuration. ...

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... FLEX 10KE devices in all packages to interface with systems of differing supply voltages. These devices have one set of V pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). 42 value and are required for 3.3-V PCI compliance. CCIO is CCIO is 2 pin CCIO CC Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet The VCCINT pins must always be connected to a 2.5-V power supply. With a 2.5-V V level, input voltages are compatible with 2.5-V, 3.3- CCINT V, and 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or 3.3-V power supply, depending on the output requirements. When the VCCIO pins are connected ...

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... IDCODE information for FLEX 10KE devices. 44 Table 16. FLEX 10KE Boundary-Scan Register Length Device EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K130E EPF10K200E EPF10K200S TM STAPL Description Boundary-Scan Register Length 690 798 1,050 1,308 1,446 Table 15. Tables 16 and 17 Altera Corporation ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Table 17. 32-Bit IDCODE for FLEX 10KE Devices Device Version Part Number (16 Bits) (4 Bits) EPF10K30E 0001 0001 0000 0011 0000 EPF10K50E 0001 0001 0000 0101 0000 EPF10K50S EPF10K100E 0010 0000 0001 0000 0000 ...

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... Update register clock to output JSCO t Update register high impedance to valid output JSZX t Update register valid output to high impedance JSXZ t t JPSU JPH t JPCO t JSH t t JSCO JSXZ Min 100 Altera Corporation t JPXZ Max Unit ...

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... AMB T Junction temperature J Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Each FLEX 10KE device is functionally tested. Complete testing of each configurable static random access memory (SRAM) bit and all logic functionality ensures 100% yield. AC test measurements for FLEX 10KE ...

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... V 2.70 (2.70) V –0.5 5. CCIO 0 70 ° C –40 85 ° ° C –40 100 ° Min Max Unit 2.625 V (2.625) 3.60 (3.60) V 2.625 V (2.625) –0.5 5. CCIO 0 70 ° C –40 85 ° ° C –40 100 ° Altera Corporation ...

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... Input pin leakage I current I Tri-stated I/O pin OZ leakage current I V supply current CC0 CC (standby) R Value of I/O pin pull- CONF up resistor before and during configuration Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Conditions 1.7, 0 – 3.00 V (9) CCIO I = –0 3.00 V (9) CCIO I = – ...

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... 1.0 MHz 1.0 MHz OUT Sheet. must rise monotonically 2.5 V, and 3.3 V. CCINT CCIO Min Max and V CCINT Tables 20 meet the relationship shown V and V CCIO CCINT by an external source. CCIO Altera Corporation Unit are CCIO and 21. ...

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... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Figure 22 shows the required relationship between V 3.3-V PCI compliance. Figure 22. Relationship between V 2.7 V (V) CCINT II 2.5 2.3 3.0 Figure 23 shows the typical output drive characteristics of FLEX 10KE devices with 3.3-V and 2.5-V V 3.3-V PCI Local Bus Specification, Revision 2.2 connected to 3.3 V). FLEX 10KE devices with a -1 speed grade also comply with the drive strength requirements of the Revision 2 ...

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... Current (mA Output Voltage ( register clock-to-output delay (t Interconnect delay (t SAMEROW LE look-up table delay (t LE register setup time (t Note ( Room Temperature Output Voltage ( LUT ) 2.5 V CCINT = 3.3 V CCIO Altera Corporation ...

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... Figure 24. FLEX 10KE Device Timing Model Dedicated Clock/Input Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Timing simulation and delay prediction are available with the Altera Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and post-synthesis timing simulation with 0 ...

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... Carry-In Data-In Control-In 54 Cascade-In LUT Delay t LUT t RLUT t CLUT Packed Register Delay t PACKED Register Control Delay Carry Chain Delay t CGENR t CASC t CGEN t CICO t t LABCARRY LABCASC Carry-Out Cascade-Out Register Delays Data-Out COMB PRE t CLR Altera Corporation ...

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... EAB Clock Delay Input Register Clock t EABCLK Output Register Clock Read Enable Input Delays t EABRE1 RE t EABRE2 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Output Data I/O Register Delay t IOD I/O Element Contol Delay t IOC Input Register Delay I/O Register t IOFD ...

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... Dedicated Clock CLRN Output Register D CLRN Input Register D CLRN through 28 describe the FLEX 10KE device internal timing Tables 29 through 30 describe the FLEX 10KE external timing Note (1) Parameter PRN Q t XZBIDIR t ZXBIDIR t OUTCOBIDIR PRN Bidirectional Q Pin t INSUBIDIR t INHBIDIR PRN Q Altera Corporation Condition ...

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... IOE input pad and buffer to IOE register delay INREG t IOE register feedback delay IOFD t IOE input pad and buffer to FastTrack Interconnect delay INCOMB Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) Parameter Note (1) Parameter CCIO CCIO CCIO CCIO ...

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... Address hold time with respect to the falling edge of the read enable RAH t Write enable to data output valid delay WO t Data-in to data-out valid delay DD t Data-out delay EABOUT t Clock high time EABCH t Clock low time EABCL 58 Note (1) Parameter Conditions (5) (5) (5) (5) Altera Corporation ...

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... EAB address setup time before rising edge of write pulse when not using EABWASU input registers t EAB address hold time after falling edge of write pulse when not using input EABWAH registers t EAB write enable to data output valid delay EABWO Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) (6) , Parameter Conditions 59 ...

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... PCISU t Hold time with global clock for registers used in PCI designs PCIH t Clock-to-output delay with global clock for registers used in PCI designs PCICO 60 Note (1) Parameter Parameter Conditions (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) Conditions (8) (9) (9) (9) , (9) (10) (9),(10) , (9) (10) Altera Corporation ...

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... Contact Altera Applications for test circuit specifications and test conditions. (9) This timing parameter is sample-tested only. (10) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local Bus Specification, revision 2.2. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (9) Parameter Conditions ...

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... EAB Asynchronous Read WE Address a0 Data-Out d0 EAB Asynchronous Write WE Data-In t EABWASU a0 Address Data-Out 62 and 30 show the asynchronous and synchronous timing a1 t EABAA d1 t EABWP t EABWDSU din0 t EABWCCOMB a1 din0 Tables EABRCCOMB d2 t EABWDH din1 t EABWAH a2 t EABDD din1 Altera Corporation a3 d3 dout2 ...

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... Data-Out Table 31. EPF10K30E Device LE Timing Microparameters (Part Symbol -1 Speed Grade Min t LUT t CLUT t RLUT t PACKED CICO t CGEN Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet a1 t EABDATAH t EABDATACO din2 a2 t EABDATAH t EABDATASU t EABWCREG dout0 dout1 Tables 31 through ...

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... INCOMB 64 -2 Speed Grade Max Min Max 0.1 0.1 0.6 0.8 0.0 0.0 0.3 0.4 0.4 0.4 0.6 1.0 0.8 0.9 0.8 0.9 2.5 2.5 -2 Speed Grade Max Min Max 2.4 2.8 0.3 0.4 1.0 1.1 0.0 0.0 1.4 0.4 1.0 1.1 1.9 2.3 1.4 1.8 4.4 5.2 2.7 3.1 2.7 3.1 2.2 2.6 5.2 6.0 3.4 4.1 0.8 1.3 0.8 1.3 Note (1) -3 Speed Grade Min Max 0.2 1.0 0.0 0.5 0.6 0.6 1.3 1.2 1.2 2.5 2.5 Note (1) -3 Speed Grade Min Max 3.8 0.5 1.6 0.0 1.9 0.5 1.6 3.0 2.5 7.0 4.3 4.3 3.8 8.3 5.5 2.4 2.4 Altera Corporation Unit Unit ...

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... EABCLK t EABCO t EABBYPASS t 0.9 EABSU t 0.4 EABH t 0.3 EABCLR 2 0 0.9 WDSU t 0.1 WDH t 1.7 WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 2.5 EABCL Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.7 2.0 0.6 0.7 1.1 1.3 0.4 0.4 0.8 0.9 0.4 0.4 0.0 0.0 0.3 0.3 0.5 0.6 1.0 0.4 0.3 3.2 3.8 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2 2.5 2.9 2.5 2.9 0.5 0.6 2.0 2.9 Note (1) -3 Speed Grade Min Max 2.3 0.8 1.4 ...

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... Min t EABAA t 6.4 EABRCOMB t 4.4 EABRCREG t 2.5 EABWP t 6.0 EABWCOMB t 6.8 EABWCREG t EABDD t EABDATACO t 1.5 EABDATASU t 0.0 EABDATAH t 1.3 EABWESU t 0.0 EABWEH t 1.5 EABWDSU t 0.0 EABWDH t 3.0 EABWASU t 0.5 EABWAH t EABWO 66 -2 Speed Grade Max Min Max 6.4 7.6 7.6 5.1 2.9 7.0 7.8 5.7 6.7 0.8 0.9 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 5.1 6.0 Note (1) -3 Speed Grade Unit Min Max 8.8 ns 8.8 ns 6.0 ns 3.3 ns 8.0 ns 9.0 ns 7.7 ns 1.1 ns 2.0 ns 0.0 ns 1.7 ns 0.0 ns 2.0 ns 0.0 ns 4.3 ns 0.4 ns 6.8 ns Altera Corporation ...

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... Speed Grade Min t DRR t (3) 2.1 INSU t (3) 0.0 INH t (3) 2.0 OUTCO t (4) 1.1 INSU t (4) 0.0 INH t (4) 0.5 OUTCO t 3.0 PCISU t 0.0 PCIH t 2.0 PCICO Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.8 2.4 1.5 1.8 1.5 1.8 2.2 2.6 1.5 1.8 0.1 0.2 2.0 2.4 0.7 1.0 2.7 3.4 4.7 5.8 2.7 3.4 0.3 0.4 0.8 0.8 Notes (1), -2 Speed Grade Max Min Max 8 ...

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... EPF10K50E device internal and external -2 Speed Grade Max Min Max 0.6 0.9 0.5 0.6 0.7 0.8 0.4 0.5 0.6 0.7 0.2 0.2 0.5 0.5 0.2 0.2 0.8 1.0 0.5 0.6 0.7 0.7 0.5 0.6 0.7 Notes (1), (2) -3 Speed Grade Unit Min Max 5.2 0.0 – – 2.0 7.6 9.7 9.7 – – – – Note (1) -3 Speed Grade Unit Min Max 1.3 0.8 1.1 0.6 0.9 0.3 0.8 0.3 1.4 0.8 0.9 0.8 0.8 Altera Corporation ...

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... Speed Grade Min t IOD t IOC t IOCO t IOCOMB t 1.0 IOSU t 0.3 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.0 0.5 0.6 0.5 0.6 2.5 2.5 Note (1) -2 Speed Grade Max Min Max 2.2 2.4 0.3 0.3 1.0 1.0 0.0 0.0 1.2 0.3 0.9 1.0 0.8 0.9 0.3 0.4 3.0 3.5 1.4 1.7 1 ...

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... 0.9 WDSU t 0.1 WDH t 1.7 WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 2.5 EABCL 70 -2 Speed Grade Max Min Max 1.7 2.0 0.6 0.7 1.1 1.3 0.4 0.4 0.8 0.9 0.4 0.4 0.0 0.0 0.3 0.3 0.5 0.6 1.0 0.4 0.3 3.2 3.8 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2 2.5 2.9 2.5 2.9 0.5 0.6 2.0 2.9 Note (1) -3 Speed Grade Min Max 2.7 0.9 1.8 0.6 1.2 0.6 0.0 0.5 0.8 1.4 0.6 0.5 5.1 3.9 1.5 1.4 0.2 2.7 2.9 5.0 0.3 3.9 3.9 0.8 2.5 3.9 Altera Corporation Unit ...

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... Table 42. EPF10K50E Device Interconnect Timing Microparameters Symbol -1 Speed Grade Min t DIN2IOE t DIN2LE t DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 6.4 7.6 7.6 5.1 2.9 7.0 7.8 5.7 6.7 0.8 0.9 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 5.1 6.0 -2 Speed Grade Max Min Max 3 ...

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... EPF10K100E device internal and external Note (1) -2 Speed Grade Max Min Max 0.7 1.0 0.5 0.7 0.6 0.8 0.3 0.4 0.2 0.3 0.1 0.1 0.4 0.5 (2) -3 Speed Grade Min Max 13.5 4.3 0.0 2.0 7 Notes (1), (2) -3 Speed Grade Min Max 4.3 0.0 2.0 7.3 10.1 10.1 -3 Speed Grade Min Max 1.5 0.9 1.1 0.5 0.3 0.2 0.7 Altera Corporation Unit Unit Unit ...

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... Speed Grade Min t IOD t IOC t IOCO t IOCOMB t 0.8 IOSU t 0.7 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) -2 Speed Grade Max Min Max 0.1 0.1 0.6 0.9 0.8 1.0 0.6 0.8 0.4 0.5 0.6 0.7 0.8 1.0 0.8 1.0 2.0 2.0 -2 Speed Grade Max Min Max 1.7 2.0 0.0 0.0 1.4 1.6 0.5 0.7 1.0 ...

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... Speed Grade Max Min Max 1.5 2.0 0.0 0.0 1.5 2.0 0.3 0.4 0.3 0.4 0.0 0.0 0.0 0.0 0.3 0.4 0.1 0.1 1.0 0.1 0.4 4.0 5.1 3.5 1.3 1.3 0.2 2.1 2.1 3.9 0.1 1.5 2.0 1.5 2.0 0.2 0.3 2.0 3.5 -2 Speed Grade Max Min Max 5.9 7.6 7.6 6.5 3.5 Note (1) -3 Speed Grade Min Max 2.6 0.0 2.6 0.5 0.5 0.0 0.0 0.5 0.2 1.4 0.2 0.5 6.6 4.7 1.7 1.7 0.3 2.8 2.8 5.2 0.2 2.6 2.6 0.3 2.5 4.7 Note (1) -3 Speed Grade Min Max 9.9 9.9 8.5 4.7 Altera Corporation Unit Unit ...

Page 75

... Table 49. EPF10K100E Device Interconnect Timing Microparameters Symbol -1 Speed Grade Min t DIN2IOE t DIN2LE t DIN2DATA t DCLK2IOE t DCLK2LE t SAMELAB t SAMEROW t SAMECOLUMN t DIFFROW t TWOROWS t LEPERIPH t LABCARRY t LABCASC Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 7.7 7.0 3.4 4.5 0.5 0.7 1.0 0.1 1.4 0.0 1.3 0.2 5.2 0.0 3.4 4.5 -2 Speed Grade Max Min Max 3.1 3.6 0.3 0.4 1 ...

Page 76

... Speed Grade Min Max 16.0 3.3 0.0 2.0 9.1 – – – – – – – – Notes (1), (2) -3 Speed Grade Min Max 3.3 0.0 – – 2.0 9.1 10.1 10.1 – – – – Altera Corporation Unit Unit ...

Page 77

... Table 53. EPF10K130E Device IOE Timing Microparameters Symbol -1 Speed Grade Min t IOD t IOC t IOCO t IOCOMB t 1.0 IOSU t 0.9 IOH t IOCLR t OD1 t OD2 Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Tables 52 through 58 show EPF10K130E device internal and external timing parameters. -2 Speed Grade Max Min 0.6 0.6 0.7 0.3 0.2 0.1 0.4 0.1 0.6 0.3 0.5 0.3 0.7 0.7 ...

Page 78

... Speed Grade Max Min Max 4.0 5.6 2.8 4.1 2.8 4.1 2.8 4.1 4.0 5.6 2.5 3.0 0.4 0.5 0.4 0.5 -2 Speed Grade Max Min Max 1.5 2.0 0.0 0.0 1.5 2.0 0.3 0.4 0.3 0.4 0.0 0.0 0.0 0.0 0.3 0.4 0.1 0.1 1.0 0.2 0.4 4.0 5.0 3.5 1.3 1.3 0.2 2.1 2.1 3.9 0.1 1.5 2.0 Note (1) -3 Speed Grade Min Max 7.5 5.5 5.5 5.5 7.5 4.1 0.6 0.6 Note (1) -3 Speed Grade Min Max 2.6 0.0 2.6 0.5 0.5 0.0 0.0 0.5 0.2 1.4 0.2 0.5 6.6 4.7 1.7 1.7 0.3 2.8 2.8 5.2 0.2 2.6 Altera Corporation Unit Unit ...

Page 79

... EABRCREG t 2.7 EABWP t 5.9 EABWCOMB t 5.4 EABWCREG t EABDD t EABDATACO t 0.8 EABDATASU t 0.1 EABDATAH t 1.1 EABWESU t 0.0 EABWEH t 1.0 EABWDSU t 0.2 EABWDH t 4.1 EABWASU t 0.0 EABWAH t EABWO Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.5 2.0 0.2 0.3 2.0 3.5 -2 Speed Grade Max Min Max 5.9 7.5 7.5 6.4 3.5 7.7 7.0 3.4 4.5 0.5 0.7 1.0 0.1 1.4 0.0 1.3 0.2 5.1 0.0 3.4 4.5 Note (1) -3 Speed Grade Unit Min Max 2 ...

Page 80

... Notes (1), -2 Speed Grade Max Min Max 9.0 12.0 2.1 0.0 5.0 2.0 7.0 1.1 0.0 4.0 0.5 6.0 6.2 0.0 6.0 2.0 6.9 Note (1) -3 Speed Grade Min Max 4.4 1.6 2.2 2.7 1.6 0.2 5.1 4.4 9.5 14.6 6.9 1.0 1.6 (2) -3 Speed Grade Min Max 16.0 3.0 0.0 2.0 9.2 – – – – – – – – Altera Corporation Unit Unit ...

Page 81

... LUT t CLUT t RLUT t PACKED CICO t CGEN t CGENR t CASC COMB t 0.4 SU Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min 2.4 0.0 3.0 0.0 5.0 2.0 5.6 5.6 4.0 0.5 4.6 4.6 Tables 24 through 30 Tables 59 through 65 show EPF10K200E device internal and external timing parameters. -2 Speed Grade ...

Page 82

... ZX3 t INREG t IOFD t INCOMB 82 -2 Speed Grade Max Min Max 1.1 0.5 0.6 0.5 0.6 2.5 2.5 -2 Speed Grade Max Min Max 1.6 1.9 0.3 0.3 1.6 1.9 0.5 0.6 0.9 0.8 0.2 0.2 0.6 0.7 0.1 0.2 2.5 3.0 4.4 5.3 4.4 5.3 3.9 4.8 6.3 7.6 4.8 5.7 1.5 1.8 1.5 1.8 Note (1) -3 Speed Grade Min Max 1.5 0.8 0.8 3.0 3.0 Note (1) -3 Speed Grade Min Max 2.6 0.5 2.6 0.8 1.2 1.1 0.3 0.9 0.7 3.9 7.1 7.1 6.9 10.1 7.7 2.4 2.4 Altera Corporation Unit Unit ...

Page 83

... WASU t 2.1 WAH t 2.2 RASU t 0.1 RAH EABOUT t 1.5 EABCH t 3.3 EABCL Table 62. EPF10K200E Device EAB Internal Timing Macroparameters (Part Symbol -1 Speed Grade Min t EABAA t 5.1 EABRCOMB t 4.8 EABRCREG t 3.3 EABWP Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 2.0 2.4 0.4 0.5 1.4 1.7 0.0 0 0.4 0.5 0.0 0.0 0.8 0.9 0.0 0.1 1.1 0.5 0.9 3.1 3.7 4.0 1.1 1.1 0.1 1.6 2.5 2.6 0.1 2 ...

Page 84

... LABCARRY t LABCASC 84 -2 Speed Grade Max Min Max 8.1 8.0 4.0 5.1 0.8 1.0 1.6 0.0 1.1 0.5 1.8 0.0 3.6 0.5 3.4 4.4 -2 Speed Grade Max Min Max 4.2 4.6 1.7 1.7 1.9 2.1 2.5 2.9 1.7 1.7 0.1 0.1 2.3 2.6 2.5 2.7 4.8 5.3 7.1 7.9 7.0 7.6 0.1 0.1 0.9 1.0 Note (1) -3 Speed Grade Unit Min Max 10.7 ns 10.6 ns 6.7 ns 1.3 ns 2.1 ns 0.0 ns 1.5 ns 0.6 ns 2.4 ns 0.0 ns 4.7 ns 0.7 ns 5.8 ns Note (1) -3 Speed Grade Unit Min Max 5.7 ns 2.0 ns 3.0 ns 4.0 ns 2.0 ns 0.2 ns 3.6 ns 4.1 ns 7.7 ns 11.3 ns 9.0 ns 0.2 ns 1.4 ns Altera Corporation ...

Page 85

... These parameters are specified by characterization. Table 66. EPF10K50S Device LE Timing Microparameters (Part Symbol -1 Speed Grade Min t LUT t CLUT t RLUT t PACKED CICO t CGEN Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Notes -2 Speed Grade Max Min 10.0 3.4 0.0 4.5 2.0 6.2 0.0 6.0 2.0 -2 Speed Grade Max Min 4.0 ...

Page 86

... INCOMB 86 -2 Speed Grade Max Min Max 0.1 0.1 0.5 0.8 0.5 0.6 0.6 0.6 0.3 0.4 0.6 0.6 0.4 0.5 0.8 1.0 2.5 2.5 -2 Speed Grade Max Min Max 1.3 1.3 0.3 0.4 1.7 2.1 0.5 0.6 1.0 0.5 0.2 0.2 1.2 1.2 0.7 0.8 2.7 3.0 4.7 5.7 4.7 5.7 4.2 5.3 6.2 7.5 3.5 4.2 1.1 1.3 1.1 1.3 Note (1) -3 Speed Grade Min Max 0.1 1.0 0.8 0.7 0.5 0.7 0.8 0.7 1.2 3.0 3.0 Note (1) -3 Speed Grade Min Max 1.9 0.4 2.6 0.8 1.3 0.6 0.4 1.9 1.7 4.3 7.5 7.5 7.3 9.9 5.6 1.8 1.8 Altera Corporation Unit Unit ...

Page 87

... EABCLK t EABCO t EABBYPASS t 0.7 EABSU t 0.4 EABH t 0.8 EABCLR 2 1 0.5 WDSU t 0.1 WDH t 1.0 WASU t 1.5 WAH t 1.5 RASU t 0.1 RAH EABOUT t 1.5 EABCH t 1.5 EABCL Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 1.7 2.4 0.4 0.6 1.0 1.4 0.0 0.0 0.0 0.0 0.4 0.6 0.0 0.0 0.8 1.1 0.0 0.0 1.0 0.6 1.1 2.0 2.8 2.8 1.4 0.7 0.1 1.4 2.1 2.1 0.1 2.1 2.9 2.1 2.9 0.0 0.0 2.0 2.0 Note (1) -3 Speed Grade Min Max 3.2 0.8 1.9 ...

Page 88

... Speed Grade Max Min Max 3.7 5.2 5.2 4.9 2.8 6.3 7.8 3.8 5.3 0.8 1.1 1.6 0.0 1.0 0.6 1.7 0.0 2.3 1.2 3.1 4.3 -2 Speed Grade Max Min Max 3.1 3.7 1.7 2.1 2.7 3.1 1.6 1.9 1.7 2.1 0.1 0.1 1.5 1.7 1.0 1.3 2.5 3.0 4.0 4.7 2.6 2.9 0.1 0.2 0.8 1.0 Note (1) -3 Speed Grade Unit Min Max 7.0 ns 7.0 ns 6.6 ns 3.8 ns 8.6 ns 10.6 ns 7.2 ns 1.5 ns 2.1 ns 0.0 ns 1.3 ns 0.8 ns 2.2 ns 0.0 ns 3.0 ns 1.8 ns 5.9 ns Note (1) -3 Speed Grade Unit Min Max 4.6 ns 2.7 ns 5.1 ns 2.6 ns 2.7 ns 0.2 ns 2.4 ns 2.1 ns 4.5 ns 6.9 ns 3.4 ns 0.2 ns 1.3 ns Altera Corporation ...

Page 89

... All timing parameters are described in (2) This parameter is measured without use of the ClockLock or ClockBoost circuits. (3) This parameter is measured with use of the ClockLock or ClockBoost circuits Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet Note (1) -2 Speed Grade Max Min Max 8 ...

Page 90

... Speed Grade Max Min Max 0.7 0.8 0.4 0.5 0.5 0.7 0.4 0.5 0.6 0.5 0.1 0.2 0.3 0.4 0.1 0.2 0.7 0.8 0.5 0.6 0.5 0.6 0.3 0.6 0.6 1.1 0.4 0.6 0.5 0.6 2.5 2.5 -2 Speed Grade Max Min Max 1.8 1.9 0.3 0.3 1.7 1.9 0.5 0.6 0.9 0.8 0.2 0.2 1.3 0.7 0.8 0.2 2.9 3.0 5.0 5.3 5.0 5.3 Note (1) -3 Speed Grade Unit Min Max 1.2 ns 0.6 ns 0.9 ns 0.7 ns 0.6 ns 0.3 ns 0.6 ns 0.3 ns 1.2 ns 0.8 ns 0.8 ns 0.8 ns 0.7 ns 1.5 ns 0.8 ns 0.8 ns 3.0 ns 3.0 ns Note (1) -3 Speed Grade Unit Min Max 2.6 ns 0.5 ns 2.6 ns 0.8 ns 1.2 ns 1.1 ns 0.3 ns 0.9 ns 0.4 ns 3.9 ns 7.1 ns 7.1 ns Altera Corporation ...

Page 91

... EABRE2 t EABCLK t EABCO t EABBYPASS t 0.7 EABSU t 0.4 EABH t 0.8 EABCLR 2 1 0.5 WDSU t 0.1 WDH t 1.1 WASU t 1.6 WAH t 1.6 RASU t 0.1 RAH EABOUT t 1.5 EABCH t 2.1 EABCL Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max 4.5 4.8 6.6 7.6 3.7 5.7 1.8 3.4 1.8 3.4 -2 Speed Grade Max Min Max 1.8 2.4 0.4 0.5 1.1 1.7 0.0 0 0.4 0.5 0.0 0.0 0.8 0.9 0.0 0.1 1.1 0.5 0.9 2.1 3.7 4.0 1.1 1.1 0.1 1.6 2.5 2.6 0.1 2.0 2.4 2.0 2 ...

Page 92

... Speed Grade Max Min Max 3.9 6.4 6.4 5.7 4.0 8.1 8.0 3.8 5.1 0.8 1.0 1.6 0.0 1.1 0.5 1.8 0.0 3.6 0.5 3.1 4.4 -2 Speed Grade Max Min Max 4.4 4.8 0.6 0.6 1.8 2.1 1.7 2.0 0.6 0.6 0.1 0.1 3.0 4.6 3.5 4.9 6.5 9.5 9.5 14.1 5.5 6.2 0.3 0.1 Note (1) -3 Speed Grade Unit Min Max 8.4 ns 8.4 ns 7.6 ns 5.3 ns 10.7 ns 10.6 ns 6.7 ns 1.3 ns 2.1 ns 0.0 ns 1.5 ns 0.6 ns 2.4 ns 0.0 ns 4.7 ns 0.7 ns 5.8 ns Note (1) -3 Speed Grade Unit Min Max 5.5 ns 0.9 ns 2.8 ns 2.8 ns 0.9 ns 0.2 ns 5.7 ns 6.4 ns 12.1 ns 17.8 ns 7.2 ns 0.2 ns Altera Corporation ...

Page 93

... All timing parameters are described in (2) This parameter is measured without the use of the ClockLock or ClockBoost circuits. (3) This parameter is measured with the use of the ClockLock or ClockBoost circuits. Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet -2 Speed Grade Max Min Max ...

Page 94

... FLEX 10KE devices. Table 80. FLEX 10KE K Constant Values Device EPF10K30E EPF10K50E EPF10K50S EPF10K100E EPF10K130E EPF10K200E EPF10K200S + CCACTIVE ) CC IO value, which depends on the IO Application Note 74 (Evaluating A -------------------------- - LC MHz LE K Value estimate based on typical conditions with CC should be verified during operation CC 4.5 4.8 4.5 4.5 4.6 4.8 4.6 Altera Corporation ...

Page 95

... Current (mA Frequency (MHz) Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet To better reflect actual designs, the power model (and the constant K in the power calculation equations) for continuous interconnect FLEX devices assumes that LEs drive FastTrack Interconnect channels. In contrast, the power model of segmented FPGAs assumes that all LEs drive only one short interconnect segment ...

Page 96

... POR timing information. 96 vs. Operating Frequency (Part EPF10K200E I Current (mA) 100 50 Frequency (MHz) EPF10K200S 600 400 Supply I CC Current (mA) 200 0 600 400 Supply CC 200 0 Frequency (MHz) 100 50 Frequency (MHz) rises, the device initiates a CC 100 50 Altera Corporation ...

Page 97

... Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode ...

Page 98

... Parallel data source Parallel data source BitBlaster or ByteBlasterMV download cables, or microprocessor with a Jam STAPL file or JBC file FLEX 10KE Device EPF10K30EF256 EPF10K30EF484 EPF10K50SB356 EPF10K50EF484 EPF10K50SF484 EPF10K100EF484 Table 82), chosen on the basis of the target Data Source Altera Corporation I/O Count 176 220 220 254 254 338 ...

Page 99

... Device Pin-Outs Revision History Altera Corporation FLEX 10KE Embedded Programmable Logic Devices Data Sheet See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information. The information contained in the FLEX 10KE Embedded Programmable Logic Data Sheet version 2.5 supersedes information published in previous versions ...

Page 100

... FLEX 10KE Embedded Programmable Logic Devices Data Sheet Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera 101 Innovation Drive Corporation in the U ...