cy8c3446lti-075es2 Cypress Semiconductor Corporation., cy8c3446lti-075es2 Datasheet

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cy8c3446lti-075es2

Manufacturer Part Number
cy8c3446lti-075es2
Description
Psoc? 3 Cy8c34 Family Errata Silicon Revision Es2
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
January 7, 2011
PSoC
(Datasheet Document Number: 001-53304 Rev. *H)
This document describes the preliminary errata for the PSoC 3: CY8C34 Family silicon revision ES2. Details include
errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this
document to the device’s datasheet for a complete functional description.
ES2 is marked on the package as part of the device number. See the examples below. Contact your local Cypress
Sales Representative if you have questions.
Part Numbers Affected
PSoC 3: CY8C34 Family Qualification Status
-40 C to 85 C Functionality.
Specifications only applicable when operating with ES2 silicon.
PSoC 3: CY8C34 Family Errata Summary
The following table defines the errata applicability to available PSoC 3: CY8C34 Family of devices.
Note Errata items in the table below are hyperlinked. Click on any item entry to jump to its description.
Cypress Semiconductor Corporation
January 7, 2011
1. Electrical Specifications
2. Device Features
3. Device Function
4. Brown Out
5. Delta Sigma ADC Range
6. Delta Sigma ADC Output Count
7. Delta Sigma ADC End-of-Conversion
8. Delta Sigma ADC Gain
9. Delta Sigma ADC Routing
10. MHz Oscillator Reliability
11. MHz Oscillator Startup
12. MHz External Crystal Oscillator Voltage
13. WDT Does Not Work in Low Power Modes
14. WDT Cleared Once, Does Not Time Out
15. Comparator Wakeup
16. Comparator Enable
17. LVD and Comparator Interrupt Level
18. UDB Low Power Retention
19. Low Power Mode and JTAG/SWD
20. Power System Initialization
[1] See full errata text for additional information and greater detail regarding fix status
®
3: CY8C34 Family Errata Silicon Revision ES2
CY8C3446AXI-099ES2
CY8C3446LTI-085ES2
CY8C3446LTI-075ES2
Part Number
Items
Document Number: 001-61136 Rev. *C
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
All ES2 Parts Affected
198 Champion Court
Part Number
.
Silicon Revision
San Jose
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
ES2
PSoC
,
CA 95134
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
Fix Confirmed in Production Silicon
®
3: CY8C34 Family
Fix Confirmed in ES2
Fix Confirmed in ES2
Fix Status
408.943.2600
[1]
[1]
1
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cy8c3446lti-075es2 Summary of contents

Page 1

... Sales Representative if you have questions. Part Numbers Affected Part Number CY8C3446AXI-099ES2 CY8C3446LTI-085ES2 CY8C3446LTI-075ES2 PSoC 3: CY8C34 Family Qualification Status -40  C Functionality. Specifications only applicable when operating with ES2 silicon. PSoC 3: CY8C34 Family Errata Summary The following table defines the errata applicability to available PSoC 3: CY8C34 Family of devices. ...

Page 2

... All ES2 Parts Affected ES2 All ES2 Parts Affected ES2 All ES2 Parts Affected ES2 All ES2 Parts Affected ES2 CY8C3446LTI-085ES2 ES2 All ES2 Parts Affected ES2 All ES2 Parts Affected ES2 All ES2 Parts Affected ES2 All ES2 Parts Affected ...

Page 3

Electrical Specifications PROBLEM DEFINITION ■ The listed parameters do not meet their electrical specifications. A quick summary is provided below. • ESD human body model is below specification. • Maximum current per VDDIO supply pin is below specification. • ...

Page 4

Errata Document PARAMETERS AFFECTED ■ Module Parameter and Description Absolute Max DC Specifications, ESD , Electro-Static Discharge Voltage HBM Table 11 Current per VDDIO supply pin vddio DC Specifications, Table 11-2 IDD, Execute from Flash, CPU at 3 ...

Page 5

Errata Document Module Parameter and Description IDAC DC Specifications, Table INL, Integral Non-Linearity 11-26 DNL, Differential Non-Linearity Ezs, Zero Scale Error Eg, Gain Error Mixer DC Specifications, Table V , Input Offset Voltage OS 11-30 TIA AC Specifications, BW, Input ...

Page 6

Errata Document Module Parameter and Description LCD Direct Drive DC Specifica- Icc operating current LCD tions, Table 11-37 Icc , LCD system operating current LCD Icc , LCD system operating current LCD Icc , LCD system operating current LCD Icc ...

Page 7

Device Features PROBLEM DEFINITION ■ The following features are not available. They are disabled by default. Keep in their disabled state. • External Memory Interface (EMIF) • JTAG Boundary Scan • USB memory management mode: Mode 3 (automatic memory ...

Page 8

Brown Out PROBLEM DEFINITION ■ The brown out detection circuit on ES2 silicon does not function properly and is unable to guarantee brown out detection in both active and sleep power modes. TRIGGER CONDITIONS ■ Vcca, Vccd, Vdda, Vddd ...

Page 9

Delta Sigma ADC Output Count PROBLEM DEFINITION ■ The Delta Sigma ADC outputs a count value symmetrical about 0, resulting in 2 the result is truncated to n bits, the maximum count is the same as the minimum count. ...

Page 10

Delta Sigma ADC Gain PROBLEM DEFINITION ■ Gain compensation trim values are not provided in the silicon. This results in gain errors when using the Delta Sigma ADC and a reduction in usable range. TRIGGER CONDITION(S) ■ Using the ...

Page 11

MHz Oscillator Startup PROBLEM DEFINITION ■ The MHz oscillator has reduced average gain; this results in startup failures in some devices with gain on the lower end of the distribution. This applies only when prototyping. MHz oscillator is not ...

Page 12

WDT Does Not Work in Low Power Modes PROBLEM DEFINITION ■ The Watchdog Timer (WDT) does not work in low power modes (Sleep and Hibernate). PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ NA SCOPE OF IMPACT ■ The WDT ...

Page 13

Comparator Wakeup PROBLEM DEFINITION ■ The device is unable to wake from sleep when trigged by a comparator. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ Using the comparator to wake the chip from a sleep to an active state. ...

Page 14

LVD and Comparator Interrupt Level PROBLEM DEFINITION ■ The LVD and comparator interrupts only support level trigger mode. Setting the LVD and comparator interrupt modes to edge mode has no effect. See the PSoC 3: CY8C34 Family Technical Reference ...

Page 15

Low Power Mode and JTAG/SWD PROBLEM DEFINITION ■ If the JTAG/SWD interfaces are enabled, the device does not enter any of the low power modes. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ JTAG/SWD interface enabled. SCOPE OF IMPACT ■ ...

Page 16

Analog Low Power Routing PROBLEM DEFINITION ■ Placing the device into sleep or hibernate mode, calling Stop() APIs for the DeltaSigma ADC, or not calling Start() APIs for the DeltaSigma ADC component causes the analog components connections to the ...

Page 17

SWD ACK PROBLEM DEFINITION ■ When reading the acknowledge response of a SWD transaction, an ACK will return a '011b' value rather then the expected '001b'. A value of '011b' traditional means a parity error, however in ES2 silicon ...

Page 18

SWO Pin PROBLEM DEFINITION ■ When the device is configured with Single Wire Debug (SWD) as the debug port, P1[3] is automatically configured for SWO and cannot be used as a GPIO. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ ...

Page 19

Configurable XRES Pin PROBLEM DEFINITION ■ When reading the NV Latches, the CNVL_XRESMEN bit glitches to ‘0’, thus resetting the device if the configurable XRES pin is enabled. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ Reading the status of ...

Page 20

Segment LCD Vddio Restriction PROBLEM DEFINITION ■ If segment LCD drive is enabled, then all Vddio supplies must be greater than or equal to the LCD bias voltage (Vbias = V0). PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ Vddio0, ...

Page 21

VIDAC0 Operation PROBLEM DEFINITION ■ VIDAC0 does not operate correctly when its output is greater than 2 either voltage or current mode. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ Use of VIDAC0 with an output voltage greater ...

Page 22

VDAC Output PROBLEM DEFINITION ■ VDAC output produces a glitch 100 ns on every DAC output update. PARAMETERS AFFECTED ■ NA TRIGGER CONDITIONS(S) ■ DAC output update. SCOPE OF IMPACT ■ VDAC output produces a glitch ...

Page 23

IDAC Current Consumption PROBLEM DEFINITIO ■ Using a VIDAC in IDAC mode causes an increase in current consumption of approximately the chip due to setting of the IDAC bit. The CapSense component, which includes an embedded ...

Page 24

SIO Increased Current Consumption PROBLEM DEFINITION ■ Each SIO pin may cause additional Vddio current in some use cases. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ SIO pin’s voltage exceeds its ...

Page 25

SIO Port Registers PROBLEM DEFINITION ■ Reading and writing to the SIO port registers with the DMA causes incorrect data to be written to or read from the port register. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ Reading and ...

Page 26

Interrupts PROBLEM DEFINITION ■ When two or more interrupts of different priorities are enabled at the same time and the higher priority interrupt triggers at approximately the same time that the lower priority interrupt being serviced returns, the lower ...

Page 27

USB EP0 Transaction Failures PROBLEM DEFINITION ■ Transfers through USB EP0 may fail. These failures manifest as STALL and Data Toggle errors. PARAMETERS AFFECTED ■ None. TRIGGER CONDITION(S) ■ Any USB transfer through EP0. SCOPE OF IMPACT ■ Causes ...

Page 28

USB Suspend PROBLEM DEFINITION ■ If USB is enabled and the chip enters hibernate or sleep mode the D+ and D- pins are both pulled high with 5 k resistors in violation of the USB specification for suspend mode. ...

Page 29

Power Mode Available PROBLEM DEFINITION ■ 2 Setting the unavailable via the PM.AVAIL.CR4 register (0x43C4) causes the Delta Sigma ADC to return inaccurate data. Setting this bit to unavailable results in reduced ...

Page 30

Reading ECC PROBLEM DEFINITION ■ When reading ECC data (0x80000-0x81FFF) with the CPU on a device in debug mode, a value of 0x00 is returned. PARAMETERS AFFECTED ■ NA TRIGGER CONDITION(S) ■ Reading ECC information while in debug mode. ...

Page 31

DMA Intraspoke Bursts PROBLEM DEFINITION ■ Intraspoke DMA transfers are limited to a one byte burst length. TRIGGER CONDITION(S) ■ Intraspoke DMA transfer configured for greater than one byte burst length. SCOPE OF IMPACT ■ Data becoming corrupted during ...

Page 32

Document History Page ® Document Title: PSoC 3: CY8C34 Family Errata Silicon Revision ES2 Document Number: 001-61136 Orig. of Submission Revision ECN Change ** 2921477 RLRM *A 2964144 RLRM *B 3043361 RLRM *C 3121790 RLRM 01/07/2011 January 7, 2011 Errata ...

Page 33

... PSoC and CapSense are registered trademarks of Cypress Semiconductor Corporation. PSoC Designer and CapSense ExpCypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

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