z80180 ZiLOG Semiconductor, z80180 Datasheet
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z80180 Summary of contents
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... Z80180 Microprocessor Unit Product Specification PS014004-1106 PS014004-1106 ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126 Telephone: 408.558.8500 • Fax: 408.558.8300 • www.zilog.com ...
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This publication is subject to replacement by a later edition. To determine whether a later edition exists request copies of publications, contact: ZiLOG Worldwide Headquarters 532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.zilog.com ZiLOG ...
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Revision History Each instance in the following table reflects a change to this document from its previous revision. To see more detail, click the appropriate link in the table below. Revision Date Level Description November 04 Updated DC Characteristics table ...
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PS014004-1106 Microprocessor Unit iv ...
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Table of Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DMA Source Address Register Channel DMA Source Address Register, Channel ...
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... Overview Features The key features of Z80180 • Code compatible with ZiLOG Z80 • Extended instructions • Two DMA channels • Low power-down modes • On-chip interrupt controllers • Three on-chip wait-state generators • On-chip oscillator/generator • Expanded MMU addressing ( MB) • ...
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... All signals with an overline are active Low. For example, B/W, in which WORD is active Low); and B/W, in which BYTE is active Low. Power connections follow conventional descriptions as listed in Table 1. Power Connection Conventions Connection Power Ground Processor Power Controller 16-Bit Programmable Reload Timers (2) Figure 1. Z80180 Functional Block Diagram PS014004-1106 Circuit Device GND V SS ...
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... INT2 A10 A11 A12 A13 A14 A15 A16 A17 A18 V CC Figure 2. Z80180 64-Pin Dip Configuration PS014004-1106 1 64 PHI MREQ IORQ RFSH HALT TEND1 DREQ1 CKS RXS/CTS1 TXS CKA1/TEND0 Z80180 RXA1 64-Pin TXA1 CKA/DREQ0 ...
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... Z80180 68-Pin PLCC Pin Configuration 9 INT0 10 INT1 INT2 A10 A11 26 27 Figure 3. Z80180 68-Pin PLCC Configuration PS014004-1106 Z80180 68-Pin PLCC 44 43 Z80180 Microprocessor Unit 4 HALT TENDi DREQi CKS RXS/CTS1 TXS CKA1/TEND0 RXA1 TEST TXA1 CKA0/DREQ0 ...
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... IORQ MREQ PHI XTAL N/C EXTAL WAIT BUSACK BUSREQ RESET 1 Figure 4. Z80180 80-Pin QFP Configuration Table 2. Pin Status During RESET BUSACK and SLEEP Pin Number and Package Type Default QFP PLCC DIP Function NMI 2 NC PS014004-1106 ...
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... GND GND OUT Z80180 Microprocessor Unit SLEEP GND Overview 6 ...
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... OUT IN OUT OUT IN IN DREQ0 3T OUT 1 OUT IN IN TEND0 OUT CTS1 I OUT Z80180 Microprocessor Unit SLEEP GND OUT IN OUT OUT IN IN OUT IN I Overview 7 ...
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... OUT OUT GND GND GND GND OUT OUT OUT OUT is not available in DIP versions of the Z80180. Microprocessor Unit SLEEP 0 OUT 1 1 OUT OUT GND GND OUT IN IN OUT IN IN —A –A form a 20-bit address bus. ...
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... Enable Clock (output, active High). Synchronous machine cycle clock output during bus E— transactions. External Clock Crystal (input, active High). Crystal oscillator connections. An EXTAL— external clock can be input to the Z80180 on this pin when a crystal is not used. This input is Schmitt-triggered. — HALT HALT/SLEEP ...
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... MREQ M1 IORQ indicates that the address MREQ operation. This signal is WRITE demands a higher prior- NMI indicated that the CPU wants indicates that the current MREQ RFSH ) contain the refresh address. A7–A10 Overview Z80180 10 sig- IOE , M1 HALT LIR ...
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... PRT channel 1. This T OUT indicated to the MPU that the addressed memory or WAIT input is sampled high, at which time execution continues. WAIT indicated that the CPU data bus holds valid WR Z80180 Microprocessor Unit and output to M1 HALT is multiplexed with TEND0 level ...
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... During RESET, this pin is initialized as RXS pin. If CTS1E bit in ASCI status register ch1 (STAT1) is set to 1, CTS1 function is selected. If CTS1E bit is set to 0, RXS function is selected. PS014004-1106 on page 21). Several pins are used for different conditions, OUT Z80180 Microprocessor Unit function is Overview 12 ...
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... Z80 Memory Management Unit— (logically only 64 KB) into the 1-MB addressing range supported by the Z80180. The orga- nization of the MMU object code allows maintenance compatibility with the Z80 CPU, while offering access to an extended memory space. This organization is achieved by using an effective common area-banked area scheme. Central Processing Unit— ...
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... Figure 6. Timer Data Register channel provides a half-duplex serial transmitter and CSIO is used for both TRDR CSIO is receiving data, a does not work. CSIO CSIO Z80180 Microprocessor Unit 0001h 0000h 0003h Reload Timer Data Register READ Timer Control Requestor READ transmission and reception ...
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... CNTR (8) Interrupt Request Operation Modes ® Z80 versus 64180 Compatibility The Z80180 is descended from two different ancestor processors, ZiLOG's original Z80 and the Hitachi 64180. The Operating Mode Control Register (OMCR), illustrated in certain Z80 and 64180 differences Figure 8. Operating Control Register (OMCR: I/O Address = 3Eh) M1E (M1 Enable)— ...
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... On the Z80180, this choice makes the processor fetch a when fetching a are not fully Z80-timing compatible but are compatible with the on-chip CTCs. When , the processor does not drive M1E = 0 fetching a instruction one time only, with normal timing, the processor goes back and ...
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... Z64180 and signals match the timing of the Z80. The IORQ Microprocessor Unit Opcode Fetch signals set RESET (Figure 11 (see Figure 12 Architecture Z80180 17 . When ...
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... HALT Opcode Address HALT M1 MREQ RD PS014004-1106 The Z80180 can operate in five modes with The Z80180 processor is fetching and running a program. All enabled instruction. Thereafter, the Z80180 HALT pins all Low. The oscillator and PHI mode in response to a Low on HALT , or an enabled external request on ...
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... INT0 INT1 If an interrupt source is individually disabled, it cannot bring the Z80180 out of mode interrupt source is individually enabled, and the globally enabled (by an return address being the instruction after the vidually enabled, but the tion), the Z80180 leaves This provides a technique for synchronization with high- speed external events without incurring the latency imposed by an interrupt response sequence ...
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... PHI SLEEP ) cannot generate a recovery interrupt. Figure 15). From Output Under Test 250 100 pF µA Symbol Value V –0 –0 opr Microprocessor Unit mode except that internal I/O sources CLOCK +5 V 2.1k Table 5 are exceeded. Unit V +0.3 V °C Architecture Z80180 20 SYS- , ...
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... Table 5. Absolute Maximum Ratings(continued) Item Extended Temperature Storage Temperature Note: Normal operation must be under recommended operating conditions. If these conditions are exceeded, it affects reliability of LSI. DC Characteristics Table 6 lists the DC characteristics of Z80180 Table 6. DC Characteristics Symbol Item V Input H Voltage IH1 RESET, EXTAL, NMI V Input H Voltage Except ...
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... CC ILmax ** 10 over specified temperature range, unless otherwise noted Characteristics Table 7, Table 8, and Z80180-6, Z80180-8, and Z80180-10, respectively 10 – 0 °C to +70 °C, unless otherwise noted. SS Table 7. Z80180-6 AC Characteristics No Symbol Item 1 t Clock Cycle Time ...
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... Table 7. Z80180-6 AC Characteristics (continued) No Symbol Item 20 t WAIT Hold Time from Ø Fall Ø Rise to Data Float Delay WDZ 22 t Ø Rise to WR Fall Delay WRD1 23 t Ø Fall to WRITE Data Delay Time WDD 24 t WRITE Data Set-up Time to WR Fall ...
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... Table 7. Z80180-6 AC Characteristics (continued) No Symbol Item 55 t Ø Fall to Timer Output Delay TOD 56 t CSIO Transmit Data Delay Time (Internal Clock STDI Operation CSIO Transmit Data Delay Time (External Clock STDE Operation CSIO Receive Data Set-up Time (Internal Clock ...
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... Table 8. Z80180-8 AC Characteristics (continued) No Symbol Item 8 t Ø Fall to MREQ Fall Delay MED1 9 t Ø Fall to RD Fall Delay RDD1 Ø Rise to RD Rise Delay 10 t Ø Rise to M1 Fall Delay M1D1 11 t Address Hold Time from AH (MREQ, IOREQ, RD, WR Ø Fall to MREQ Rise Delay ...
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... Table 8. Z80180-8 AC Characteristics (continued) No Symbol Item 32 t INT Hold Time from Ø Fall INTS 33 t NMI Pulse Width NMIW 34 t BUSREQ Set-up Time to Ø Fall BRS 35 t BUSREQ Hold Time from Ø Fall BRH 36 t Ø Rise to BUSACK Fall Delay BAD1 ...
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... Table 8. Z80180-8 AC Characteristics (continued) No Symbol Item 58 t CSIO Receive Data Set-up Time (Internal Clock SRSI Operation CSIO Receive Data Hold Time (Internal Clock SRHI Operation CSIO Receive Data Set-up Time (External Clock SRSE Operation CSIO Receive Data Hold Time (External Clock ...
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... Table 9. Z80180-10 AC Characteristics (continued) No Symbol Item 8 t Ø Fall to MREQ Fall Delay MED1 9 t Ø Fall to RD Fall Delay RDD1 Ø Rise to RD Rise Delay 10 t Ø Rise to M1 Fall Delay M1D1 11 t Address Hold Time from AH (MREQ, IOREQ, RD, WR Ø Fall to MREQ Rise Delay ...
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... Table 9. Z80180-10 AC Characteristics (continued) No Symbol Item 32 t INT Hold Time from Ø Fall INTS 33 t NMI Pulse Width NMIW 34 t BUSREQ Set-up Time to Ø Fall BRS 35 t BUSREQ Hold Time from Ø Fall BRH 36 t Ø Rise to BUSACK Fall Delay BAD1 ...
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... Table 9. Z80180-10 AC Characteristics (continued) No Symbol Item 58 t CSIO Receive Data Set-up Time (Internal Clock SRSI Operation CSIO Receive Data Hold Time (Internal Clock SRHI Operation CSIO Receive Data Set-up Time (External Clock SRSE Operation CSIO Receive Data Hold Time (External Clock ...
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... Figure 16. CPU Timing (Opcode Fetch, I/O WRITE, and I/O READ Cycles) PS014004-1106 Z80180 Microprocessor Unit 31 Architecture ...
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... INTi 33 NMI MI *1 IORQ *1 Date IN *1 MREQ *2 RFSH * BUSREQ BUSACK ADDRESS DATA MREQ, RD WR, IORQ HALT Figure 17. CPU Timing (INT0 Acknowledge Cycle, Refresh Cycle) PS014004-1106 Z80180 Microprocessor Unit Architecture 32 ...
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... CPU Timin= 0) (I/O READ Cycle, I/O WRITE Cycle φ ADDRESS IROQ RD WR Figure 18. CPU Timing (IOC = 0) (I/O READ Cycle, I/O WRITE Cycle) PS014004-1106 I/O WRITE Cycle I/O READ Cycle CPU Timing (IOC=0) I/O READ Cycle I/O WRITE Cycle Z80180 Microprocessor Unit Architecture 33 ...
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... DRQS DHQH 3. DMA cycle starts. 4. CPU cycle starts. PS014004-1106 CPU or DMA READ/WRITE Cycle (Only DMA WRITE Cycle for TENDi Figure 19. DMA Control Signals Z80180 Microprocessor Unit Architecture 34 ...
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... E Clock Timing (Minimum timing example Example I/O READ → Opcode Fetch Figure 22. E Clock Timing (P PS014004-1106 and P WEL WEH Z80180 Microprocessor Unit Minimum Timing) Architecture 35 ...
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... Reg.=0000h OUT Execution Cycle SLEEP Instruction fetch ø INTi NMI A – MREQ HALT PS014004-1106 55 Figure 23. Timer Output Timing Figure 24. SLEEP Execution Cycle Z80180 Microprocessor Unit Next Opcode fetch Architecture 36 ...
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... The following sections explain the various functions of the ASCI registers. Figure 27 displays the ASCI block diagram. PS014004-1106 11t 11t cyc cyc 58 59 16.5t 11.5t 11.5t cyc cyc IH1 V IL1 Figure 26. Rise Time and Fall Times Microprocessor Unit 58 59 16.5t cyc cyc 61 69 Exter- nal Architecture Z80180 37 ...
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... If no data is TDR TSR s by outputting a continuous High level. This TSR IDLE . Data written to the ASCI Transmit Data Register is as soon as is empty. Data can be written while TSR TSR Z80180 Microprocessor Unit TXA 1 RXA 1 CTS 1 Note: *Not Program Accessible. ...
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... ASCI transmit data for channel 0 and channel 1, 06h 07h — —- — — — — — ASCI Transmit Channel 0 Figure 28. ASCI Register Channel 0 Z80180 Microprocessor Unit This register receives data shifted The ASCI Receive 08h 09h while the FIFO is full. RSR Architecture 39 ...
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... ASCI Transmit Channel 1 Figure 29. ASCI Register Channel 1 and hold the ASCI receive data for channel 0 and channel 1, 08h 09h — — — — — — — — ASCI Receive Data Z80180 Microprocessor Unit 40 Architecture ...
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... MP CNTLB ), exhibits no effect. If multiprocessor mode is selected, CNTLB = 0 MPE , only received bytes in which the Microprocessor Unit 1 0 MOD1 MOD0 R/W R MOD1 MOD0 R/W R/W is set multiprocessor mode is not 1 (multiprocessor bit) = can affect MPB 1 ) are ignored by the MPB = 0 Architecture Z80180 ASCI ...
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... CNTLA1 When multiprocessor MPB , the function is selected to reset all 0 EFR register undefined 0 MPBR/EFR These bits program the ASCI , , and MOD2 MOD1 MOD0 Architecture Z80180 42 and are held. are held. bit for are ...
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... The format is as follows. ) format does not feature any provision for parity. MP=1 , MOD0 MOD1 during . RESET pin features the function, and the state of the pin can be read in bit CTS0 Z80180 Microprocessor Unit 1 0 SS1 SS0 R/W R/W data bit for transmission. If MPB is transmitted. state is ...
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... DCD0/CKA1 . 1 SS0 Divide Ratio ÷1 0 ÷2 1 ÷4 0 ÷8 1 ÷16 0 ÷32 1 ÷ External Clock Z80180 Microprocessor Unit , = 0). If bit in the System LOW 5 TDRE . 0 mode bit in the register is BRG ASEXT 0 does not affect the PEO is cleared to , even parity is PEO 0 is cleared to during ...
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... CNT1LA 1 bit in the register. However, this status bit is not set PEO CNTLB to the bit in the register, and also by 1 EFR CNTRLA pin is auto-enabled and is negated (High). DCD0 Z80180 Microprocessor Unit 1 0 TDRE TIE R R TDRE TIE R R/W is set to ...
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... TIE = 1 is used to monitor CNTR SS2 TE R/W R/W R/W Figure 35. CSIO Control Register is set to by the EF 1 CSIO Z80180 Microprocessor Unit to the 1 mode, and for ASCIO if the DCDO to enable ASCI receive 1 and are , or is SAR17–16 10 DIM1 . either ASCI RDRF RIE ...
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... When TE pin. In either CKS set and are never both set the TE RE mode. , and select the transmit/ SS1 SS0 CSIO during . Table 13 1 RESET , , SS2 SS1 SS0 = 1 Architecture Z80180 and lists ). ...
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... Figure 38. Timer Data Register Channel High PS014004-1106 — — — — — — CSIO Transmit/Receive Data — — — — — — Timer Data — — — — — — — Timer Data Z80180 Microprocessor Unit 48 Architecture ...
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... Figure 39. Timer Reload Register Low — — — — — — Timer Reload Data Figure 40. Timer Reload Register , ) status. It also controls enabling and PRT0 PRT1 TMDR TIE1 TIE0 TOC1 TOC0 R/W R/W R/W Microprocessor Unit / A18 T OUT TDE1 TDE0 R/W R/W R/W Architecture Z80180 49 for ...
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... RESET ASCI Extension Control Register Channels 0 and 1 ASEXT0 and ASEXT1 The ASCI Extension Control Register controls functions newly added to the ASCIs in the Z80180 family. Note: All bits in this register reset to 0. PS014004-1106 TMDR1 , an interrupt request is generated. TIE1 = 1 is read ...
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... TDRE and this bit is 0 register. CNTLB0 pin is received CKA pin, regardless of whether CKA pin is CKA register are not , and this bit is 111 bit in DR CNTLB pin. If are not CKA SS2–0 111 . 0 Architecture Z80180 and ...
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... ASCIO DCD0 are both Timer Data Timer Data Z80180 Microprocessor Unit bit to when an all-zero 1 . The bit is RxFIFO register, also RESET , the transmitter holds the pin Low 1 TXA , in which state carries the 0 TXA 0 0 Architecture ...
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... Mnemonic RLDR1L: 16H Timer Data Register Figure 45. Timer Reload Register Channel 1L Timer Reload Register Channel 1H Mnemonic RLDR1H: 17H Timer Data Register Figure 46. Timer Reload Register Channel 1H PS014004-1106 Reload Data Reload Data Z80180 Microprocessor Unit 0 0 Architecture 53 ...
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... PS014004-1106 Counting Data Figure 47. Timer Data Register ) specifies the physical source address for channel — — — — — — — DMA Channel 0 Address Figure 48. DMA Channel 0L Z80180 Microprocessor Unit 0 REQUEST HANDSHAKE 0 — Architecture 54 ...
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... DMA Channel 0 Address Figure 49. DMA Channel — — — — — — — — — — — — — — DMA Channel B Address Figure 50. DMA Channel 0B ) specifies the physical destination address for channel 0 Z80180 Microprocessor Unit 55 REQUEST HANDSHAKE Architecture ...
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... DMA Channel 0L Address — — — — — — — DMA Channel 0H Address — — — — DMA Channel B Address Z80180 Microprocessor Unit 0 — 0 — Architecture 56 ...
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... Z Mask, these DMA registers are expanded from 4 bits to 3 bits in the A17 A16 DMA Transfer Request 0 0 DREQ0 0 1 TDR0 (ASCI0 TDR1 (ASCI1 Not Used ) specifies the number of bytes to be transferred. This reg Counting Data Figure 54. DMA Byte Count Register 0L Z80180 Microprocessor Unit . RESET 0 Architecture 57 ...
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... DMA Byte Count Register 0H DMA Byte Count Register Channel 1L Mnemonic BCR1L: Address 2Eh DMA Byte Count Register 1L PS014004-1106 Counting Data Figure 55. DMA Byte Count Register Counting Data Figure 56. DMA Byte Count Register 1L Z80180 Microprocessor Unit 0 0 Architecture 58 ...
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... Figure 58. DMA Memory Address Register, Channel 1L PS014004-1106 Counting Data Figure 57. DMA Byte Count Register 1H ) specifies the physical memory address for channel — — — — — — — DMA Memory Address Z80180 Microprocessor Unit 0 0 — Architecture 59 ...
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... All bits in IAR1B PS014004-1106 — — — — — — — DMA Memory Address — — — — DMA Memory Channel B Address ) specifies the I/O address for channel 1 transfers, which reset Z80180 Microprocessor Unit 0 — REQUEST Architecture 60 ...
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... Figure 63. DMA I/O Address Register Channel 1H PS014004-1106 OUT Req 1 Sel DREQ — — — — — — — DMA I/O Channel 1L Address — — — — — — — — DMA I/O Address Channel 1H Z80180 Microprocessor Unit — 0 Architecture 61 ...
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... WRITE DE1 DWE1 to disables channel 1 DMA, but DMA is restartable. Writing DE1 0 during . 0 RESET DE0 = 1 BCR0 = 0 Z80180 Microprocessor Unit DSTAT 1 0 DME R and , channel 1 DMA is DME = reset to by the DMAC. DE1 DMA interrupt request is during the same register ...
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... DWE0 is set to , the DIE0 1 ) causes a CPU interrupt DE1 = 0 is set to , the DIE0 1 ) causes a CPU interrupt DE0 = 0 DE bit is set interrupt NMI (even if the allowing DMA operations DME indirectly set to NMI 0 during . 0 RESET Architecture Z80180 63 bit by 1 ...
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... I/O to/from I/O transfers are not implemented, 12 combinations are available. PS014004-1106 DM0 SM0 DM1 SM1 MMOD R/W R/W R/W R/W DM1 16). Memory Increment/Decrement +1 –1 fixed fixed Table 17). Memory Increment/Decrement +1 –1 fixed fixed Z80180 Microprocessor Unit 1 0 R/W and are cleared to during DM0 and . Because DM0 DM1 SM0 SM1 Architecture 64 ...
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... DMS1 for level sense because the device undertakes a relatively long period to signal after the DMA channel reads data from it in the first of the two operation to it, as the WRITE Z80180 Microprocessor Unit signal to control the transfer MMOD = 1 REQUEST HANDSHAKE is cleared to during ...
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... PRTs (Figure 68 –– –– –– –– Interrupt Source Dependent Code Z80180 Microprocessor Unit / can use T DREQ OUT , and . These three bits are cleared CSIO 0 –– Architecture 66 ...
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... RESET TRAP Interrupt The Z80180 generates a nonmaskable (not affected by the state of when an undefined opcode fetch occurs. This feature can be used to increase software reli- ability, implement an extended instruction set, or both. cycles and also if an undefined opcode is fetched during the interrupt acknowledge cycle for when Mode 0 is used ...
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... When a interrupt occurs, the Z80180 operates as follows: TRAP 1. The bit in the Interrupt TRAP 2. The current Program Counter ( opcode, is saved on the stack. 3. The Z80180 vectors to logical address Note: If logical address 0000h is mapped to physical address 00000h, the vector is the same as for RESET. In this case, testing the TRAP bit in ITC reveals whether the restart at physical address 00000h was caused by RESET or TRAP ...
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... REFW = 0 causes the refresh cycle to be three clocks in duration by adding set to during TRW REFW 1 Microprocessor Unit Restart from 0000h Opcode Fetch Cycle 0000h SP-2 PC — Cyc0 Cyc1 during . 1 RESET . RESET Architecture Z80180 69 ...
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... Refresh cycles are suppressed when the bus is released in response to However, the refresh timer continues to operate. The time at which the first refresh cycle occurs after the Z80180 reacquires the bus depends on the refresh timer, and possesses no timing relationship with the bus exchange. ...
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... Figure 74. MMU Bank Base Register (BBR: I/O Address = 39h) PS014004-1106 CBR during . 0 RESET CB4 CB3 CB2 R/W R/W R/W are reset to BBR BB5 BB4 BB3 BB2 R/W R/W R/W R/W Microprocessor Unit specifies the base address (on 4- CB0 CB1 R/W R/W during . 0 RESET 1 0 BB1 BB0 R/W R/W Architecture Z80180 71 ...
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... MMU Common/Bank Area Register (CBAR) Mnemonic CBAR Address 3A specifies boundaries within the Z80180 64-KB logical address space for up to three CBAR areas: Common Area, Bank Area and Common Area 1. MMU Common/Bank Area Register (CBAR: I/O Address = Bit CA3 CA2 R/W R/W Figure 75. MMU Common/Bank Area Register (CBAR: I/O Address = 3 AH CA3– ...
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... When , the M1E = 1 acknowledge cycle, and the first machine cycle of the On the Z80180, this choice makes the processor fetch a when fetching a are not fully Z80-timing compatible, but are compatible with the on-chip CTCs. When , the processor does not drive ...
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... R/W during . 0 RESET 00FFh 00C0h 00BFh 0080h 0070h 0040h 003Fh 0000h Figure 79. I/O Address Relocation Mode (bit 5)— mode is enabled when IOSTOP is reprogrammed or IOSTOP Z80180 Microprocessor Unit also controls enabling/disabling of ICR 1 0 — — Figure 79. and IOA7 IOA6 is set to . Normal IOSTP RESET ...
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... Package Information Figure 80. 80-Pin QFP Package Diagram PS014004-1106 Z80180 Microprocessor Unit 75 Package Information ...
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... PS014004-1106 Figure 81. 64-Pin DIP Package Diagram Z80180 Microprocessor Unit 76 Package Information ...
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... PLCC Package Diagram Figure 82. 68-Pin PLCC Package Diagram PS014004-1106 Z80180 Microprocessor Unit 77 Package Information ...
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... P = Plastic Dual In Line V = Plastic Leaded Chip Carrier Temperature °C to +70 °C Speed MHz MHz MHz Environmental C = Plastic Standard Example: The Z80180 is a 10-MHz DIP, 0 º ºC, with Plastic Standard Flow. Z ZiLOG Prefix 80180 Product Number 10 Speed P Package S ...
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... Customer Support If you experience any problems while operating this product, please check the ZiLOG Knowledge Base: http://kb.zilog.com/kb/oKBmain.asp If you cannot find an answer or have further questions, please see the ZiLOG Technical Support web page: http://support.zilog.com PS014004-1106 Z80180 Microprocessor Unit 79 Customer Support ...