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MC68HC908QY4 MC68HC908QT4 MC68HC908QY2 MC68HC908QT2 MC68HC908QY1 MC68HC908QT1 Data Sheet M68HC08 Microcontrollers MC68HC908QY4/D Rev. 5 07/2005 freescale.com ...
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... Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...
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Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet Revision Date Level September, N/A Initial release ...
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Revision History (Sheet Revision Date Level Reformatted to meet latest M68HC08 documentation standards Figure 1-1. Block Diagram — Diagram redrawn to include keyboard interrupt module and TCLK pin designator. Figure 1-2. MCU Pin Assignments — Added TCLK ...
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Revision History Revision History (Sheet Revision Date Level Reformatted to meet current documentation standards 6.3.1 BUSCLKX4 — Clarified description of BUSCLKX4 Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary: Reworked definitions for STOP ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters 8 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.6 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 9.7 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 13.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Monitor Module (MON ...
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Table of Contents 16 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 1 General Description 1.1 Introduction The MC68HC908QY4 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is a Complex Instruction Set Computer (CISC) with a Von Neumann architecture. All MCUs in ...
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General Description • On-chip in-application programmable FLASH memory (with internal program/erase voltage generation) – MC68HC908QY4 and MC68HC908QT4 — 4096 bytes – MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and MC68HC908QT1 — 1536 bytes • 128 bytes of on-chip random-access memory (RAM) • 2-channel, 16-bit ...
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Features of the CPU08 include the following: • Enhanced HC05 programming model • Extensive loop control functions • 16 addressing modes (eight more than the HC05) • 16-bit index register and stack pointer • Memory-to-memory data transfers Fast 8 × ...
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General Description PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM V POWER SUPPLY V RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and ...
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PTA5/OSC1/KBI5 2 7 PTA4/OSC2/KBI4 6 3 PTA3/RST/KBI3 4 5 8-PIN ASSIGNMENT MC68HC908QT1 PDIP/SOIC PTB7 2 15 PTB6 3 14 PTA5/OSC1/KBI5 4 13 PTA4/OSC2/KBI4 5 12 PTB5 6 11 PTB4 ...
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General Description 1.5 Pin Functions Table 1-2 provides a description of the pin functions. Pin Name V Power supply DD V Power supply ground SS PTA0 — General purpose I/O port AD0 — A/D channel 0 input PTA0 TCH0 — ...
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Pin Function Priority Table 1-3 is meant to resolve the priority if multiple functions are enabled on a single pin. Upon reset all pins come up as input ports regardless of the priority table. Table 1-3. Function Priority in ...
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General Description 24 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 2 Memory 2.1 Introduction The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: • 4096 bytes of user FLASH for MC68HC908QT4 and MC68HC908QY4 • 1536 bytes of user ...
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Memory $0000 I/O REGISTERS ↓ 64 BYTES $003F $0040 RESERVED ↓ 64 BYTES $007F $0080 RAM ↓ 128 BYTES $00FF $0100 UNIMPLEMENTED ↓ 9984 BYTES $27FF $2800 AUXILIARY ROM ↓ 1536 BYTES $2DFF $2E00 UNIMPLEMENTED ↓ 49152 BYTES $EDFF $EE00 ...
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Input/Output (I/O) Section Addresses $0000–$003F, shown in Additional I/O registers have these addresses: • $FE00 — Break status register, BSR • $FE01 — Reset status register, SRSR • $FE02 — Break auxiliary register, BRKAR • $FE03 — Break flag ...
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Memory Addr. Register Name Unimplemented $0006 ↓ $000A Unimplemented Read: Port A Input Pullup Enable $000B Register (PTAPUE) Write: See page 99. Reset: Read: Port B Input Pullup Enable $000C Register (PTBPUE) Write: See page 102. Reset: $000D ↓ Unimplemented ...
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Addr. Register Name Read: TIM Counter Register Low $0022 (TCNTL) Write: See page 128. Reset: Read: TIM Counter Modulo $0023 Register High (TMODH) Write: See page 129. Reset: Read: TIM Counter Modulo $0024 Register Low (TMODL) Write: See page 129. ...
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Memory Addr. Register Name $0039 ↓ Unimplemented $003B Read: ADC Status and Control $003C Register (ADSCR) Write: See page 45. Reset: $003D Unimplemented Read: ADC Data Register $003E (ADR) Write: See page 47. Reset: Read: ADC Input Clock Register $003F ...
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Addr. Register Name Read: FLASH Control Register $FE08 (FLCR) Write: See page 33. Reset: Read: Break Address High $FE09 Register (BRKH) Write: See page 136. Reset: Read: Break Address low $FE0A Register (BRKL) Write: See page 136. Reset: Read: Break ...
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Memory Vector Priority Lowest Highest 2.5 Random-Access Memory (RAM) Addresses $0080–$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. For correct operation, ...
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FLASH Memory (FLASH) This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an ...
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Memory ERASE — Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal set the same time. 1 ...
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FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block ...
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Memory (minimum 30 µs). 8. Wait for time, t PROG 9. Repeat step 7 and 8 until all desired bytes within the row are programmed. (1) 10. Clear the PGM bit . (minimum 5 µs). 11. Wait for time, t ...
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Algorithm for Programming a Row (32 Bytes) of FLASH Memory NOTES: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step ...
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Memory 2.6.6 FLASH Block Protect Register The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines ...
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Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The ...
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Memory 40 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 3 Analog-to-Digital Converter (ADC) 3.1 Introduction This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to- digital converter. The ADC module is only available on the MC68HC908QY2, MC68HC908QT2, MC68HC908QY4, and MC68HC908QT4. 3.2 Features Features of ...
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Analog-to-Digital Converter (ADC) PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM POWER SUPPLY RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source ...
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INTERNAL DATA BUS READ DDRA WRITE DDRA WRITE PTA READ PTA CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK Freescale Semiconductor DDRAx RESET PTAx ADC DATA REGISTER ADC VOLTAGE IN ADCVIN ADC ADC CLOCK CLOCK GENERATOR ADIV[2:0] Figure 3-2. ADC ...
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Analog-to-Digital Converter (ADC) 3.3.2 Voltage Conversion When the input voltage to the ADC equals V voltage equals V the ADC converts it to $00. Input voltages between V SS, linear conversion. All other input voltages will result in $FF if ...
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Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before using ...
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Analog-to-Digital Converter (ADC) AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when ADR is read or ADSCR is written. Reset clears ...
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ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: $003E Bit 7 Read: AD7 Write: Reset: 3.7.3 ADC Input Clock Register This register selects the clock frequency for ...
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Analog-to-Digital Converter (ADC) 48 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 4 Auto Wakeup Module (AWU) 4.1 Introduction This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. AWU. 4.2 Features Features of ...
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Auto Wakeup Module (AWU) COPRS (FROM CONFIG1) INT RC OSC EN 32 kHz CLRLOGIC CLEAR (CGMXCLK) CLK BUSCLKX4 RST RESET Figure 4-1. Auto Wakeup Interrupt Request Generation Logic The auto wakeup RC oscillator is highly dependent on operating voltage and ...
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Input/Output Registers The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The following I/O registers control and monitor operation of the AWU: • Port A data register (PTA) • Keyboard interrupt status ...
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Auto Wakeup Module (AWU) Bits 7–4 — Not used These read-only bits always read as 0s. KEYF — Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears ...
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Chapter 5 Configuration Register (CONFIG) 5.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enable or disable the following options: Stop mode recovery time (32 × BUSCLKX4 cycles or • 4096 × BUSCLKX4 cycles) • ...
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Configuration Register (CONFIG) IRQPUD — IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and V IRQEN — IRQ Pin Function Selection Bit 1 = Interrupt request function active ...
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LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module LVI module power disabled 0 = LVI module power enabled LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the ...
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Configuration Register (CONFIG) 56 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 6 Computer Operating Properly (COP) 6.1 Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by ...
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Computer Operating Properly (COP) The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 262,128 or 8176 BUSCLKX4 ...
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COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Chapter 5 Configuration Register 6.4 COP Control Register The COP control register (COPCTL) is located ...
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Computer Operating Properly (COP) 60 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 7 Central Processor Unit (CPU) 7.1 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction ...
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Central Processor Unit (CPU 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 Read: Write: Reset: 7.3.2 Index Register The ...
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Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least ...
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Central Processor Unit (CPU) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following ...
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Z — Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00 Zero result 0 = Non-zero result C — Carry/Borrow Flag The CPU sets the ...
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Central Processor Unit (CPU) 7.7 Instruction Set Summary Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form Branch if Higher or Same BHS rel (Same as BCC) BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT #opr BIT opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form CLR opr CLRA CLRX CLRH Clear CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X Compare A with M ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine JSR opr,X JSR ,X LDA #opr LDA opr ...
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Central Processor Unit (CPU) Table 7-1. Instruction Set Summary (Sheet Source Operation Form PULA Pull A from Stack PULH Pull H from Stack PULX Pull X from Stack ROL opr ROLA ROLX Rotate Left through Carry ROL ...
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Table 7-1. Instruction Set Summary (Sheet Source Operation Form SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr TSTA TSTX Test for Negative or Zero TST ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...
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Chapter 8 External Interrupt (IRQ) 8.1 Introduction The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interrupt (KBI), provides a maskable interrupt input 8.2 Features Features of the IRQ module include the following: • External interrupt ...
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External Interrupt (IRQ) PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM V DD POWER SUPPLY V SS RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High ...
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ACK RESET VECTOR FETCH DECODER V DD IRQPUD INTERNAL PULLUP DEVICE IRQ 8.3.1 MODE = 1 If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set, both of the ...
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External Interrupt (IRQ) 8.4 Interrupts The following IRQ source can generate interrupt requests: • Interrupt flag (IRQF) — The IRQF bit is set when the IRQ pin is asserted based on the IRQ mode. The IRQ interrupt mask bit, IMASK, ...
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IRQ Input Pins (IRQ) The IRQ pin provides a maskable external interrupt source. The IRQ pin contains an internal pullup device. 8.8 Registers The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. See ...
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External Interrupt (IRQ) 78 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 9 Keyboard Interrupt Module (KBI) 9.1 Introduction The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are accessible via the PTA0–PTA5 pins. 9.2 Features Features of the keyboard interrupt module include: • Six keyboard interrupt pins ...
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Keyboard Interrupt Module (KBI) PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM POWER SUPPLY RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and ...
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KBI0 . KBIE0 . TO PULLUP ENABLE . KBI5 KBIE5 TO PULLUP ENABLE (1) 1. For AWUGEN logic refer to AWUIREQ Figure 9-2. Keyboard Interrupt Block Diagram If the MODEK bit is set, the keyboard interrupt inputs are both falling ...
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Keyboard Interrupt Module (KBI) To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and then read the data register. Setting a keyboard interrupt enable bit (KBIEx) forces ...
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To protect the latch during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state ...
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Keyboard Interrupt Module (KBI) 9.7.2 Keyboard Interrupt Enable Register The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wakeup to operate as a keyboard interrupt input. Address: $001B Bit 7 Read: 0 ...
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Chapter 10 Low-Voltage Inhibit (LVI) 10.1 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V and can force a reset when the V 10.2 Features Features of the LVI module include: • Programmable ...
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Low-Voltage Inhibit (LVI Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. TRIPF Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, V for ...
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LVI Status Register The LVI status register (LVISR) indicates if the V LVI resets have been disabled . Address: $FE0C Bit 7 Read: LVIOUT Write: Reset Unimplemented Figure 10-2. LVI Status Register (LVISR) LVIOUT — LVI Output ...
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Low-Voltage Inhibit (LVI) 88 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 11 Oscillator Module (OSC) 11.1 Introduction The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by ...
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Oscillator Module (OSC) PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM POWER SUPPLY RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source ...
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Internal Oscillator Trimming The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and –128 steps. Increasing OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to 12.8 MHz ± 5%. ...
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Oscillator Module (OSC) 11.3.3 XTAL Oscillator The XTAL oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. ...
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RC Oscillator The RC oscillator circuit is designed for use with an external resistor (R a tolerance within 25% of the expected frequency. See The capacitor (C) for the RC oscillator is internal to the MCU. The R 1% ...
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Oscillator Module (OSC) 11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output. For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The ...
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SIM and results in the internal bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK frequency. 11.5 Low Power Modes The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 11.5.1 ...
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Oscillator Module (OSC) 11.8.1 Oscillator Status Register The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock sources. Address: $0036 Bit 7 Read: R Write: Reset Reserved R Figure 11-4. Oscillator Status Register ...
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Chapter 12 Input/Output Ports (PORTS) 12.1 Introduction The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have five bidirectional input-output (I/O) pins and one input only pin. The MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4 have thirteen bidirectional pins and one input only pin. All I/O pins ...
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Input/Output Ports (PORTS) 12.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins. Address: $0000 Bit 7 Read: R Write: Reset: Additional Functions: R PTA[5:0] — Port ...
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Figure 12-3 shows the port A I/O logic. READ DDRA ($0004) WRITE DDRA ($0004) WRITE PTA ($0000) READ PTA ($0000) When DDRAx reading address $0000 reads the PTAx data latch. When DDRAx reading address ...
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Input/Output Ports (PORTS) PTAPUE[5:0] — Port A Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port A pins Corresponding port A pin configured to have internal pull if its DDRA bit ...
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Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing DDRB bit enables the output buffer for the corresponding port B pin; a ...
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Input/Output Ports (PORTS) 12.3.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the ...
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Chapter 13 System Integration Module (SIM) 13.1 Introduction This section describes the system integration module (SIM), which supports external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. ...
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System Integration Module (SIM) STOP/WAIT CONTROL V DD CLOCK CONTROL INTERNAL PULL-UP RESET POR CONTROL PIN LOGIC RESET PIN CONTROL SIM RESET STATUS REGISTER INTERRUPT CONTROL AND PRIORITY DECODE 13.2 RST and IRQ Pins Initialization RST and IRQ pins come ...
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OSCILLATOR OSCILLATOR 13.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 13.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals ...
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System Integration Module (SIM) 13.4.1 External Pin Reset The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long ...
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Reset Recovery Type 13.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles ...
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System Integration Module (SIM) 13.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM ...
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SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery ...
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System Integration Module (SIM) YES (AS MANY INTERRUPTS AS EXIST ON CHIP) 110 FROM RESET YES BREAK INTERRUPT? I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO YES TIMER INTERRUPT? NO LOAD PC WITH INTERRUPT VECTOR FETCH ...
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MODULE INTERRUPT I BIT ADDRESS BUS DUMMY SP DATA BUS DUMMY R/W MODULE INTERRUPT I BIT ADDRESS BUS SP – 4 DATA BUS R/W 13.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware ...
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System Integration Module (SIM) INT1 INT2 Figure 13-10 13.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. A software interrupt ...
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Interrupt Status Register 1 Address: $FE04 Bit 7 Read: 0 Write: R Reset Reserved Figure 13-11. Interrupt Status Register 1 (INT1) IF1 and IF3–IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from ...
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System Integration Module (SIM) 13.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 13.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break ...
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A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, ...
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System Integration Module (SIM) The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery then used to time the recovery period. Figure 13-18 shows the stop mode recovery ...
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SIM Reset Status Register The SRSR register contains flags that show the source of the last reset. The status register will automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in ...
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System Integration Module (SIM) 13.8.2 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: $FE03 Bit 7 Read: BCFE Write: Reset: ...
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Chapter 14 Timer Interface Module (TIM) 14.1 Introduction This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions block diagram of ...
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Timer Interface Module (TIM) PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM POWER SUPPLY RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and ...
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Functional Description Figure 14-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference ...
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Timer Interface Module (TIM) 14.4.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, ...
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TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, ...
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Timer Interface Module (TIM) 14.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over ...
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PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. ...
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Timer Interface Module (TIM) 14.6 Wait Mode The WAIT instruction puts the MCU in low power-consumption standby mode. The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the ...
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TIM Status and Control Register The TIM status and control register (TSC) does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • Prescales the TIM counter ...
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Timer Interface Module (TIM) TRST — TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the ...
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TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 ...
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Timer Interface Module (TIM) Address: $0025 TSC0 Bit 7 Read: CH0F Write: 0 Reset: 0 Address: $0028 TSC1 Bit 7 Read: CH1F Write: 0 Reset Unimplemented Figure 14-7. TIM Channel Status and Control CHxF — Channel x Flag ...
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When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Reset clears the MSxA bit Initial output level low 0 = Initial output level high Before changing a channel function by ...
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Timer Interface Module (TIM) CHxMAX — Channel x Maximum Duty Cycle Bit When the TOVx bit setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 14-8 or ...
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Chapter 15 Development Support 15.1 Introduction This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods. 15.2 Break Module (BRK) The break module can generate a break interrupt that stops normal program flow ...
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Development Support PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 8-BIT ADC 128 BYTES RAM V POWER SUPPLY V RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and ...
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When the internal address bus matches the value written in the break address registers or when software writes the BRKA bit in the break status and control register, the CPU starts a break interrupt by: • Loading ...
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Development Support 15.2.2.1 Break Status and Control Register The break status and control register (BRKSCR) contains break module enable and status bits. Address: $FE0B Bit 7 Read: BRKE Write: Reset Unimplemented Figure 15-3. Break Status and Control Register ...
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Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU state of break interrupt with monitor mode. Address: $FE02 Bit 7 Read: 0 Write: Reset: ...
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Development Support 15.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: $FE03 Bit 7 Read: BCFE Write: Reset ...
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Functional Description Figure 15-9 shows a simplified diagram of monitor mode entry. The monitor module receives and executes commands from a host computer. and Figure 15-12 show example circuits used to enter monitor mode and communicate with a host ...
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Development Support MAX232 µ C1– C2 µF 6 V– 5 C2– 1 µF DB9 Figure 15-10. Monitor Mode Circuit (External Clock, ...
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MAX232 µ C1– C2 µF 6 V– 5 C2– 1 µF DB9 Figure 15-12. Monitor Mode Circuit (Internal Clock, No High Voltage) ...
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Development Support Table 15-1. Monitor Mode Signal Requirements and Options IRQ RST Reset Mode (PTA2) (PTA3) Vector Normal TST DD Monitor $FFFF (blank) Forced Monitor $FFFF (blank) Not User X X ...
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If monitor mode was entered with V IRQ. 15.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when ...
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Development Support Modes Reset Vector High User $FFFE Monitor $FEFE 15.3.1.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical. START BIT 0 BIT 1 BIT ...
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The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of ...
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Development Support Table 15-4. WRITE (Write Memory) Command Description Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data Operand byte Data Returned None Opcode $49 FROM HOST WRITE WRITE ECHO Table 15-5. IREAD (Indexed Read) ...
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Table 15-7. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Returns incremented stack pointer value ( Data Returned high-byte:low-byte order Opcode $0C FROM HOST ECHO Table 15-8. RUN (Run User Program) Command Description Executes ...
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Development Support 15.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. ...
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Chapter 16 Electrical Specifications 16.1 Introduction This section contains electrical and timing specifications. 16.2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. This device is not ...
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Electrical Specifications 16.3 Functional Operating Range Characteristic Operating temperature range Operating voltage range 16.4 Thermal Characteristics Characteristic Thermal resistance 8-pin PDIP 8-pin SOIC 8-pin DFN 16-pin PDIP 16-pin SOIC 16-pin TSSOP I/O pin power dissipation (1) Power dissipation (2) Constant ...
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DC Electrical Characteristics (1) Characteristic Output high voltage I = –2.0 mA, all I/O pins Load I = –10.0 mA, all I/O pins Load I = –15.0 mA, PTA0, PTA1, PTA3–PTA5 only Load Maximum combined I (all I/O ...
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Electrical Specifications 16.6 Typical 5-V Output Drive Characteristics 2.0 1.5 1.0 0.5 0.0 0 Figure 16-1. Typical 5-Volt Output High Voltage 2.0 1.5 1.0 0.5 0.0 0 Figure 16-2. Typical 5-Volt Output Low Voltage 152 -5 -10 -15 -20 -25 ...
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Control Timing Characteristic Internal operating frequency Internal clock period (1 RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period 4.5 to 5.5 Vdc Vdc, ...
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Electrical Specifications 16.8 5-V Oscillator Characteristics Characteristic (1) Internal oscillator frequency Deviation from trimmed Internal oscillator 12.8 MHz, fixed voltage, fixed temp ± 10 70°C 12.8 MHz ± 10%, –40 to 125°C 12.8 MHz ...
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DC Electrical Characteristics (1) Characteristic Output high voltage I = –0.6 mA, all I/O pins Load I = –4.0 mA, all I/O pins Load I = –10.0 mA, PTA0, PTA1, PTA3–PTA5 only Load Maximum combined I (all I/O ...
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Electrical Specifications 16.10 Typical 3.0-V Output Drive Characteristics 1.5 1.0 0.5 0.0 0 Figure 16-5. Typical 3-Volt Output High Voltage 1.5 1.0 0.5 0.0 0 Figure 16-6. Typical 3-Volt Output Low Voltage 156 -5 -10 -15 IOH (mA) versus Output ...
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Control Timing Characteristic Internal operating frequency Internal clock period (1 RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period 2.7 to 3.3 Vdc Vdc, ...
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Electrical Specifications 16.12 3-V Oscillator Characteristics Characteristic (1) Internal oscillator frequency Deviation from trimmed Internal oscillator 12.8 MHz, fixed voltage, fixed temp ± 10 70°C 12.8 MHz ± 10%, –40 to 125°C 12.8 MHz ...
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Supply Current Characteristics (1) Characteristic (3) Run Mode V supply current DD (4) Wait Mode V supply current DD (5) Stop Mode V supply current DD –40 to 85°C –40 to 105°C –40 to 125°C 25°C with auto wakeup ...
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Electrical Specifications Figure 16-10. Typical 3-Volt Run Current 160 Bus Frequency (MHz) Figure 16-9. Typical 5-Volt Run Current versus ...
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Analog-to-Digital Converter Characteristics Characteristic Supply voltage Input voltages Resolution (1 LSB) Absolute accuracy (Total unadjusted error) ADC internal clock Conversion range Power-up time Conversion time (1) Sample time (2) Zero input reading (3) Full-scale reading Input capacitance (3) Input ...
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Electrical Specifications 16.15 Timer Interface Module Characteristics Characteristic Timer input capture pulse width Timer input capture period Timer input clock pulse width 1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus ...
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Memory Characteristics Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH read bus clock frequency FLASH page erase time <1 k cycles >1 k cycles FLASH mass erase time FLASH PGM/ERASE to HVEN setup time FLASH high-voltage ...
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Electrical Specifications 164 MC68HC908QY/QT Family Data Sheet, Rev. 5 Freescale Semiconductor ...
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Chapter 17 Ordering Information and Mechanical Specifications 17.1 Introduction This section contains order numbers for the MC68HC908QY1, MC68HC908QY2, MC68HC908QY4, MC68HC908QT1, MC68HC908QT2, and MC69HC908QT4. Dimensions are given for: • 8-pin plastic dual in-line package (PDIP) • 8-pin small outline integrated circuit ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005. All rights reserved. ...