mc68hc908gr8a Freescale Semiconductor, Inc, mc68hc908gr8a Datasheet

Page 1

... MC68HC908GR8A MC68HC908GR4A Data Sheet M68HC08 Microcontrollers MC68HC908GR8A Rev. 5 04/2007 freescale.com ...

Page 2

...

Page 3

... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005, 2007. All rights reserved. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 3 ...

Page 4

... V DC Electrical Characteristics — Changed V 19.6 3 Electrical Characteristics — Changed V 19.15.1 CGM Component Specifications — Corrected and updated values 19.15.2 CGM Electrical Specifications — Corrected and updated values 19.17 Memory Characteristics — Updated memory characteristics table MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Description max to 8.5 V TST max to 8 ...

Page 5

... Chapter 5 Configuration Register (CONFIG) CGMXCLK and corrected what set and cleared indicate for bit April, 5 CONFIG1_COPRS 2007 10.6.2 Stop Mode MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Description — Replaced COPCLK with — Replaced COPCLK with CGMXCLK Page Number(s) 248 ...

Page 6

... Revision History MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...

Page 7

... Chapter 15 Serial Peripheral Interface (SPI) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Chapter 16 Timebase Module (TBM 195 Chapter 17 Timer Interface Module (TIM1 and TIM2 199 Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . 249 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 7 ...

Page 8

... List of Chapters MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...

Page 9

... FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.6.4 FLASH Mass Erase Operation 2.6.5 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.6.6 FLASH Block Protection 2.6.7 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.6.8 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6.9 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 1 General Description and and DDA SSA ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CGMXFC ...

Page 10

... Oscillator Stop Mode Enable Bit (OSCSTOPENB 4.4.8 Crystal Output Frequency Signal (CGMXCLK 4.4.9 CGM Base Clock Output (CGMOUT 4.4.10 CGM CPU Interrupt (CGMINT MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 3 Analog-to-Digital Converter (ADC) )/ADC Voltage Reference Low Pin (V SSAD )/ADC Voltage Reference High Pin (V DDAD ) ...

Page 11

... COPRS (COP Rate Select 6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2 Features MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Configuration Register (CONFIG) Chapter 6 Chapter 7 Central Processor Unit (CPU) 11 ...

Page 12

... Analog-to-Digital Converter (ADC 105 10.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 10.3 Break Module (BRK 106 10.3.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.3.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 8 External Interrupt (IRQ) Chapter 9 Keyboard Interrupt Module (KBI) Chapter 10 Low-Power Modes Freescale Semiconductor ...

Page 13

... Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.3.2 Forced Reset Operation 112 11.3.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.3.4 LVI Trip Selection 113 11.4 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 11 Low-Voltage Inhibit (LVI) 13 ...

Page 14

... Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 13.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 13.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 12 Input/Output (I/O) Ports Chapter 13 Freescale Semiconductor ...

Page 15

... Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 14.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.7.1 SIM Break Status Register 171 14.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 14 System Integration Module (SIM) 15 ...

Page 16

... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16.6 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Timer Interface Module (TIM1 and TIM2) 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 17.2 Features 201 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 15 Chapter 16 Timebase Module (TBM) Chapter 17 Freescale Semiconductor ...

Page 17

... Monitor Module (MON 221 18.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 18.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 18.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.3.1.6 Baud Rate 226 18.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 18.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 18 Development Support 17 ...

Page 18

... CGM Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.15.2 CGM Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 19.16 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 19.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Ordering Information and Mechanical Specifications 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.2 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 20.3 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Chapter 19 Electrical Specifications Chapter 20 Freescale Semiconductor ...

Page 19

... This document also describes the MC68HC908GR4A. The MC68HC908GR4A is a device identical to the MC68HC908GR8A except that it has less FLASH memory. Only when there are differences from the MC68HC908GR8A is the MC68HC908GR4A specifically mentioned in the text. ...

Page 20

... General Description • Master reset pin and power-on reset (POR) • 7680 bytes of on-chip FLASH memory on the MC68HC908GR8A and 4096 byes of on-chip FLASH memory on the MC68HC908GR4A with in-circuit programming capabilities of FLASH program memory. • 384 bytes of on-chip random-access memory (RAM) • ...

Page 21

... POWER V DDA V SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT BREAK MODULE DUAL VOLTAGE ...

Page 22

... PTE0/TxD PTE1/RxD PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK Figure 1-2. 32-Pin LQFP Pin Assignments NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the LQFP. Figure 1-3. 28-Pin DIP and SOIC Pin Assignments MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev RST IRQ 4 5 ...

Page 23

... It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Chapter 14 System Integration Module (SIM). 1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Chapter 8 External Interrupt (IRQ). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor and ...

Page 24

... Chapter 15 Serial Peripheral Interface (SPI) These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev and V ...

Page 25

... Any unused inputs and I/O ports should be tied to an appropriate logic level (either require termination, termination is recommended to reduce the possibility of static damage. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 13 Serial Communications Interface (SCI) Ports. NOTE ). Although the I/O ports of the MC68HC908GR8A do not Pin Functions 25 ...

Page 26

... General Description MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...

Page 27

... Chapter 2 Memory 2.1 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • 7680 bytes of user FLASH memory on the MC68HC908GR8A or 4096 bytes of user FLASH memory on the MC68HC908GR4A • 384 bytes of random-access memory (RAM) • 544 bytes of FLASH burn-in routines in ROM • ...

Page 28

... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev I/O REGISTERS ↓ 64 BYTES ↓ 384 BYTES UNIMPLEMENTED ↓ 6720 BYTES RESERVED FOR INTEGRATED FLASH BURN-IN ROUTINES ↓ 544 BYTES UNIMPLEMENTED ↓ ...

Page 29

... Note: $FFF6–$FFFD contains 8 security bytes $FFFE $FFFF Figure 2-1. Memory Map (Continued) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) ...

Page 30

... Reserved Write: $000B Reset: Read: Data Direction Register E $000C (DDRE) Write: See page 128. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Bit Unaffected by reset 0 0 PTB5 ...

Page 31

... SCI Status Register 1 $0016 (SCS1) Write: See page 151. Reset: Read: SCI Status Register 2 $0017 (SCS2) Write: See page 153. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit ...

Page 32

... Register (T1SC) Write: See page 209. Reset: Read: Timer 1 Counter $0021 Register High (T1CNTH) Write: See page 210. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Bit ...

Page 33

... Register (T2SC) Write: See page 211. Reset: Read: Timer 2 Counter $002C Register High (T2CNTH) Write: See page 210. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit Bit ...

Page 34

... Register (PMSH) Write: See page 68. Reset: Read: PLL Multiplier Select Low $0039 Register (PMSL) Write: See page 69. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Bit Bit ...

Page 35

... Register (SBFCR) Write: See page 220. Reset: Read: Interrupt Status Register 1 $FE04 (INT1) Write: See page 167. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit VRS7 VRS6 VRS5 VRS4 0 1 ...

Page 36

... Register (FLBPR) Write: See page 44. Reset: 1. Non-volatile FLASH register Read: COP Control Register $FFFF (COPCTL) Write: See page 81. Reset: Figure 2-2. Control, Status, and Data Registers (Sheet MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Bit IF14 IF13 IF12 IF11 ...

Page 37

... Vector Priority Lowest Highest MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor . Table 2-1. Vector Addresses Vector Address $FFDC Timebase Vector (High) IF16 $FFDD Timebase Vector (Low) $FFDE ADC Conversion Complete Vector (High) IF15 $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) ...

Page 38

... Functional Description The FLASH memory is an array of 7,680 bytes for the MC68HC908GR8A or 4,096 bytes for the MC68HC908GR4A with an additional 36 bytes of user vectors and one byte of block protection. An erased bit reads as 1 and a programmed bit reads Memory in the FLASH array is organized into two rows per page basis ...

Page 39

... This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal set the same time Program operation selected 0 = Program operation unselected MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 6 5 ...

Page 40

... Clear the HVEN bit. (typical 1 μs), the memory can be accessed in read mode again. 10. After a time, t RCV 1. When in monitor mode, with security sequence failed (see of any FLASH address. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE (1) within the FLASH memory address range. NOTE 18 ...

Page 41

... Care must be taken within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF highly recommended that interrupts be disabled during program/ erase operations. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE (Figure 2-4 NOTE ...

Page 42

... The FLASH block protect register is not protected with special hardware or software. Therefore, if this page is not protected by FLBPR the register is erased by either a page or mass erase operation. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE maximum or t maximum. t ...

Page 43

... PROG This row program algorithm assumes the row programmed are initially erased. Figure 2-4. FLASH Programming Flowchart MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 1 SET PGM BIT 2 READ THE FLASH BLOCK PROTECT REGISTER 3 ...

Page 44

... Figure 2-6. FLASH Block Protect Start Address Table 2-2. Examples of Protect Address Ranges BPR[7:0] $00 $81 (1000 0001) $82 (1000 0010) $FC (1111 1100) $FD (1111 1101) $FE (1111 1110) $FF MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev BPR6 BPR5 BPR4 BPR3 Unaffected by reset. Initial value from factory is 1. ...

Page 45

... FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH minimum. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE FLASH Memory (FLASH) ...

Page 46

... Memory MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...

Page 47

... I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a 0. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ). ...

Page 48

... SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device Figure 3-1. Block Diagram Highlighting ADC Block and Pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT ...

Page 49

... V DDA REFH Connect the V DDA connect the V SSA V pin should be routed carefully for maximum noise immunity. DDA MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor DDRBx PTBx ADC DATA REGISTER ADC VOLTAGE IN (V ADIN V ADC ...

Page 50

... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ADC cycles ...

Page 51

... In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor )/ADC Voltage Reference Low Pin (V ...

Page 52

... If any unused channels are selected, the resulting ADC conversion will be unknown or reserved. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE Table 3-1. NOTE Table 3-1. Mux Channel Select ADCH2 ADCH1 ADCH0 ...

Page 53

... ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source Internal bus clock 0 = Oscillator output clock (CGMXCLK) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 6 5 ...

Page 54

... Analog-to-Digital Converter (ADC) The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See f ADIC MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev bus frequency CGMXCLK = ADIV[2:0] 19 ...

Page 55

... Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK. Figure 4-1 shows the structure of the CGM. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 55 ...

Page 56

... PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER RDS3–RDS0 V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL11–MUL0 CGMVDV FREQUENCY DIVIDER MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev CGMRCLK BCS CGMXFC V SSA VPR1–VPR0 VRS7–VRS0 VOLTAGE LOOP CONTROLLED FILTER OSCILLATOR PLL ANALOG AUTOMATIC ...

Page 57

... The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor , (38.4 kHz) times a linear factor, L, and a power-of-two factor Modes ...

Page 58

... The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below f . BUSMAX MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev 4.5.2 PLL Bandwidth Control 4.3.8 Base Clock Selector Circuit.) The PLL is automatically in Register read-only indicator of the mode of Modes ...

Page 59

... R with RCLK practical choices of f RCLK R = round R MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Specifications), after turning on the PLL by setting PLLON in the PLL , after entering tracking mode before selecting the PLL as the AL NOTE . ...

Page 60

... Select a VCO linear range multiplier, L, where f 9. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, f center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. For proper operation, MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev × ⎛ ⎞ ...

Page 61

... In the PLL reference divider select register (PMDS), program the binary coded equivalent of R. Table 4-1 provides numeric examples (numbers are in hexadecimal notation): f (MHz) f BUS 2.0 4.0 8.0 2.0 4.0 8.0 2.4576 4.9152 7.3728 2.0 4.0 8.0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor VCLK NOTE Table 4-1. Numeric Example PCTL (MHz) RCLK 4.0 ...

Page 62

... Filter network Routing should be done with great care to minimize signal cross talk and noise. See 19.15 Clock Generation Module Characteristics MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev 4.3.6 Programming the PLL Circuit.) for capacitor and resistor values. does not account for three possible ...

Page 63

... The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor CGMXCLK CGMXFC OSC2 R ...

Page 64

... CGMOUT percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 4.4.10 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev DDA NOTE ...

Page 65

... When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only. Figure 4-3. CGM I/O Register Summary MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Register.) High.) Low.) Register ...

Page 66

... CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ...

Page 67

... In manual operation, forces the PLL into acquisition or tracking mode Address: $0037 Bit 7 Read: AUTO Write: Reset Unimplemented Figure 4-5. PLL Bandwidth Control Register (PBWC) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Circuit.) PLL.) PRE1 and PRE0 cannot be written when the PLLON bit is set 4.3.6 Programming the ...

Page 68

... Reset initializes the registers to $0040 for a default multiply value of 64. The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] — Unimplemented Bits These bits have no function and always read as 0s. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ...

Page 69

... VRS7–VRS0 — VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (see 4.3.3 PLL Circuits, 4.3.6 Programming the hardware center-of-range frequency, f PCTL is set. (See 4.3.7 Special Programming MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor MUL6 MUL5 MUL4 ...

Page 70

... When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Exceptions.). Reset initializes the register to ...

Page 71

... The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE 14.7.1 SIM Break Status Register ...

Page 72

... External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev 4.3.3 PLL Circuits, Register ...

Page 73

... CGMXFC (A) V SSA Table 4-4. Example Filter Component Values f RCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Time, the external filter network is critical to the Figure 4-10(A). Refer to Table 4-4 ( Figure 4-10. PLL Filter 8.2 nF 820 pF 4 ...

Page 74

... Clock Generator Module (CGM) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...

Page 75

... Upon a reset, the CONFIG registers default to predetermined settings as shown in Address: $001E Bit 7 6 Read Write: Reset Unimplemented Figure 5-1. Configuration Register 2 (CONFIG2) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure 5-1 and Figure ...

Page 76

... LVIRSTD disables the reset signal from the LVI module. See 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. See 1 = LVI module power disabled 0 = LVI module power enabled MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev LVIRSTD ...

Page 77

... STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. See 1 = COP module disabled 0 = COP module enabled MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 11 Low-Voltage Inhibit NOTE NOTE Chapter 6 Computer Operating Properly (COP) ...

Page 78

... Configuration Register (CONFIG) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Freescale Semiconductor ...

Page 79

... COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1) 1. See Chapter 14 System Integration Module (SIM) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor SIM MODULE 12-BIT SIM COUNTER COP CLOCK COP MODULE 6-BIT COP COUNTER CLEAR COP COUNTER for more details ...

Page 80

... Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up. 6.3.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev NOTE . During the break state, TST ...

Page 81

... Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 6 ...

Page 82

... STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset. 6.8 COP Module During Break Mode The COP is disabled during a break interrupt when V MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev present on the RST pin. TST ...

Page 83

... Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes • Low-power stop and wait modes 7.3 CPU Registers Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 83 ...

Page 84

... The index register can serve also as a temporary data storage location. Bit Read: Write: Reset Indeterminate MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ACCUMULATOR ( INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC ...

Page 85

... During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit Read: Write: Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...

Page 86

... N — Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result Negative result 0 = Non-negative result MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ...

Page 87

... CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Arithmetic/Logic Unit (ALU) ...

Page 88

... BGT opr Operands) BHCC rel Branch if Half Carry Bit Clear BHCS rel Branch if Half Carry Bit Set BHI rel Branch if Higher MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Description ← (A) + (M) + (C) A ← (A) + (M) SP ← (SP) + (16 « – – – – – – IMM M) H:X ← ...

Page 89

... CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC Clear Carry Bit CLI Clear Interrupt Mask MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC rel ? ( – – – – – – REL PC ← (PC rel ? IRQ = 1 – ...

Page 90

... EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX Increment INC opr,X INC ,X INC opr,SP MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Description ← $00 A ← $00 X ← $00 H ← $00 0 – – – M ← $00 M ← $00 M ← ...

Page 91

... ORA opr,SP ORA opr,SP PSHA Push A onto Stack PSHH Push H onto Stack PSHX Push X onto Stack MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Effect on CCR Description ← Jump Address – – – – – – PC ← (PC Push (PCL) ...

Page 92

... SUB #opr SUB opr SUB opr SUB opr,X Subtract SUB opr,X SUB ,X SUB opr,SP SUB opr,SP MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev Effect on CCR Description ← (SP + 1); Pull (A) – – – – – – INH SP ← (SP + 1); Pull (H) – ...

Page 93

... M Memory location N Negative bit 7.8 Opcode Map See Table 7-2. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Description ← (PC Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) – – 1 – – – INH SP ← ...

Page 94

Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 5 ...

Page 95

... The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only (MODE = 0), the interrupt remains set until a vector fetch, software clear, or reset occurs. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 95 ...

Page 96

... The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. Addr. Register Name Read: IRQ Status and Control $001D Register (INTSCR) Write: See page 98. Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev CLR IMASK MODE Figure 8-1. IRQ Module Block Diagram ...

Page 97

... To protect CPU interrupt flags during the break state, write the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Support ...

Page 98

... MODE — IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev ...

Page 99

... If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 99 ...

Page 100

... SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device Figure 9-1. Block Diagram Highlighting KBI Block and Pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 100 INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT ...

Page 101

... Return of all enabled keyboard interrupt pins to a high level — As long as any enabled keyboard interrupt pin is low, the keyboard interrupt remains set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ACKK V ...

Page 102

... The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes. 9.5.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 102 NOTE Freescale Semiconductor ...

Page 103

... Keyboard interrupt pending keyboard interrupt pending ACKK — Keyboard Acknowledge Bit Writing this write-only bit clears the keyboard interrupt request. ACKK always reads as 0. Reset clears ACKK. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 9.7.1 Keyboard Status and Control 6 5 ...

Page 104

... Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 104 ...

Page 105

... The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 ...

Page 106

... CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the OSCSTOPENB bit in the CONFIG2 register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 106 Freescale Semiconductor ...

Page 107

... Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Computer Operating Properly Module (COP) ...

Page 108

... The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 108 Freescale Semiconductor ...

Page 109

... Low-voltage inhibit (LVI) reset — A power supply voltage below the V and loads the program counter with the contents of locations $FFFE and $FFFF. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Timer Interface Module (TIM1 and TIM2) voltage resets the MCU ...

Page 110

... Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. Use the full stop recovery time (SSREC = 0) in applications that use an external crystal unless the OSCSTOPENB bit is set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 110 NOTE Freescale Semiconductor ...

Page 111

... V TRIPR 0 V which will re-trigger the power-on reset and reset the trip point to 3-V operation. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor voltage falls below the LVI trip falling voltage voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI ...

Page 112

... In applications that require V DD module to reset the MCU when V LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 112 for details of the LVI’s configuration bits. Once an LVI rises above a voltage, V ...

Page 113

... LVI Interrupts The LVI module does not generate interrupt requests. 11.6 Low-Power Modes The STOP and WAIT instructions put the MCU in low power-consumption standby modes. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor fall below V ), the LVI will maintain a reset condition until ...

Page 114

... If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 114 Freescale Semiconductor ...

Page 115

... See page 122. Reset: Read: Port D Data Register $0003 (PTD) Write: See page 124. Reset: Read: Data Direction Register A $0004 (DDRA) Write: See page 118. Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Bit PTB5 ...

Page 116

... Port C Input Pullup Enable $000E Register (PTCPUE) Write: See page 124. Reset: Read: Port D Input Pullup Enable $000F Register (PTDPUE) Write: See page 127. Reset: Figure 12-1. I/O Port Register Summary (Continued) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 116 Bit DDRB5 DDRB4 ...

Page 117

... The port A data register (PTA) contains a data latch for each of the four port A pins. Address: $0000 Bit 7 Read: 0 Write: Reset: Alternative Function: = Unimplemented MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor DDR Module Control DDRA0 KBIE0 DDRA1 KBIE1 KBD DDRA2 KBIE2 ...

Page 118

... Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from Figure 12-4 shows the port A I/O logic. READ DDRA ($0004) WRITE DDRA ($0004) WRITE PTA ($0000) READ PTA ($0000) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 118 Chapter 9 Keyboard Interrupt Module (KBI ...

Page 119

... These writeable bits are software programmable to enable pullup devices on an input port bit Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-2 summarizes the operation of the port A pins. ...

Page 120

... DDRB bit enables the output buffer for the corresponding port B pin disables the output buffer. Address: $0005 Bit 7 Read: 0 Write: Reset Unimplemented Figure 12-7. Data Direction Register B (DDRB) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 120 PTB5 PTB4 PTB3 Unaffected by reset ...

Page 121

... X Input, Hi Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE DDRBx RESET PTBx Figure 12-8. Port B I/O Circuit Table 12-3 summarizes the operation of the port B pins. ...

Page 122

... Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from For those devices packaged in a 28-pin DIP or SOIC package, PTC1–PTC0 are not connected. Set DDRC1 and DDRC0 configure PTC1–PTC0 as outputs. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 122 ...

Page 123

... Don’t care 2. I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor DDRCx RESET PTCx Figure 12-11. Port C I/O Circuit Table 12-4 summarizes the operation of the port C pins. ...

Page 124

... D. Reset has no effect on port D data. T2CH0 — Timer 2 Channel I/O Bit The PTD6/T2CH0 pin is a TIM2 input capture/output compare pin. The edge/level select bits, ELSxB:ELSxA, determine whether the PTD6/T2CH0 pin is a timer channel I/O pin or a general-purpose I/O pin. See MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 124 ...

Page 125

... Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Chapter 17 Timer Interface Module (TIM1 and Table 12-5 ...

Page 126

... Don’t care 2. I/O pin pulled internal pullup device Writing affects data register, but does not affect input. 4. Hi-Z = High impedance MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 126 DDRDx RESET PTDx Figure 12-15. Port D I/O Circuit Table 12-5 summarizes the operation of the port D pins. ...

Page 127

... Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the ESCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 6 5 ...

Page 128

... Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from Figure 12-19 shows the port E I/O logic. READ DDRE ($000C) WRITE DDRE ($000C) WRITE PTE ($0008) READ PTE ($0008) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 128 Module. Module ...

Page 129

... X Input, Hi Output Don’t care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 12-6 summarizes the operation of the port E pins. Table 12-6. Port E Pin Functions Accesses to DDRE Read/Write (2) DDRE1–DDRE0 DDRE1– ...

Page 130

... Input/Output (I/O) Ports MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 130 Freescale Semiconductor ...

Page 131

... Noise error – Framing error – Parity error • Receiver framing error detection • Hardware parity checking • 1/16 bit-time noise detection • Mask option register bit, SCIBDSRC, to allow selection of baud rate clock source MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 131 ...

Page 132

... SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device Figure 13-1. Block Diagram Highlighting SCI Block and Pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 132 INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT ...

Page 133

... The SCI uses the standard non-return-to-zero mark/space data format illustrated in START BIT 0 BIT 1 BIT START BIT BIT 0 BIT 1 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-1 Table 13-1. Pin Name Conventions Generic Pin Names: RxD Full Pin Names: PTE1/RxD 8-BIT DATA FORMAT ...

Page 134

... WAKEUP CONTROL SCIBDSRC FROM ENSCI CONFIG2 SL CGMXCLK A ÷ SCALER BUS CLOCK => SCICLK = CGMXCLK => SCICLK = BUS CLOCK MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 134 INTERNAL BUS LOOPS RECEIVE FLAG CONTROL CONTROL BKF RPF PRE- BAUD DIVIDER DATA SELECTION ÷ ...

Page 135

... The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Bit 7 ...

Page 136

... BUS CLOCK => SCICLK = CGMXCLK => SCICLK = BUS CLOCK PRE- ÷ 4 SCALER SCP1 SCP0 SCR2 SCR1 SCR0 TRANSMITTER CPU INTERRUPT REQUEST MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 136 INTERNAL BUS BAUD ÷ 16 SCI DATA REGISTER DIVIDER SHIFT REGISTER TXINV ...

Page 137

... Clears the SCI data register (SCDR) • Clears the R8 bit in SCC3 • Sets the break flag bit (BKF) in SCS2 • May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Functional Description 137 ...

Page 138

... SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 138 NOTE ...

Page 139

... => SCICLK = CGMXCLK => SCICLK = BUS CLOCK BKF RPF WAKE ILTY PEN ERROR CPU PTY INTERRUPT REQUEST Figure 13-6. SCI Receiver Block Diagram MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS SCR2 SCR1 SCR0 PRE- BAUD ÷ 16 DIVIDER DATA PTE1/RxD ...

Page 140

... RT3, RT5, and RT7 Start bit verification is not successful if any two of the three verification samples are 1s. If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 140 13-7): START BIT ...

Page 141

... FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-3. Data Bit Recovery ...

Page 142

... RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 142 Figure ...

Page 143

... If they are not the same, software can set the RWU bit and put the receiver back into the standby state. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...

Page 144

... CPU. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 144 NOTE Freescale Semiconductor ...

Page 145

... The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor for information on exiting wait mode. ...

Page 146

... This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit Transmitter output inverted 0 = Transmitter output not inverted Setting the TXINV bit inverts all transmitted values, including idle, break, start, and stop bits. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 146 ...

Page 147

... Changing the PTY bit in the middle of a transmission or reception can generate a parity error. Control Bits M PEN and PTY MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-5. Figure NOTE Table 13-5. Character Format Selection Character Format Start Data Parity Bits Bits 1 8 None 1 9 ...

Page 148

... PTE0/TxD returns to the idle condition (1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit Transmitter enabled 0 = Transmitter disabled MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 148 ...

Page 149

... Receiver overrun interrupts – Noise error interrupts – Framing error interrupts • Parity error interrupts Address: $0015 Bit 7 Read: R8 Write: Reset Unimplemented Figure 13-12. SCI Control Register 3 (SCC3) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE NOTE NOTE ORIE ...

Page 150

... Transfer of SCDR data to transmit shift register complete • Transmission complete • Transfer of receive shift register data to SCDR complete • Receiver input idle • Receiver overrun • Noisy data • Framing error • Parity error MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 150 Freescale Semiconductor ...

Page 151

... ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit Receive shift register full and SCRF = receiver overrun MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...

Page 152

... CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit Framing error detected framing error detected MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 152 NORMAL FLAG CLEARING SEQUENCE BYTE 2 ...

Page 153

... Polling RPF before disabling the SCI module or entering stop mode can show whether a reception is in progress Reception in progress reception in progress MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...

Page 154

... Unimplemented Figure 13-17. SCI Baud Rate Register (SCBR) SCP1 and SCP0 — SCI Baud Rate Prescaler Bits These read/write bits select the baud rate prescaler divisor as shown in and SCP0. SCP1 and SCP0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 154 ...

Page 155

... PD = prescaler divisor BD = baud rate divisor Table 13-8 shows the SCI baud rates that can be generated with a 4.9152-MHz bus clock when f selected as SCI clock source. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 13-7. SCI Baud Rate Selection Baud Rate Divisor (BD) 000 001 ...

Page 156

... MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 156 SCR2, SCR1, Baud Rate and SCR0 Divisor (BD) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 000 1 001 2 010 4 011 ...

Page 157

... SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing INTERNAL PULLUP DEVICE RESET PIN LOGIC SIM RESET STATUS REGISTER MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor STOP/WAIT CONTROL SIM COUNTER ÷ 2 CLOCK CLOCK GENERATORS CONTROL ...

Page 158

... Interrupt Status $FE05 Register 2 (INT2) Write: See page 168. Reset: Read: Interrupt Status $FE06 Register 3 (INT3) Write: See page 168. Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 158 Table 14-1. Signal Name Conventions Description Bit Writing a 0 clears SBSW. ...

Page 159

... In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor CGMXCLK CGMOUT Figure 14-3 ...

Page 160

... The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 160 14.4 SIM Counter), but an external reset does not. Each of shows the relative timing ...

Page 161

... The RST pin is driven low during the oscillator stabilization time. • The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES Figure 14-5 ...

Page 162

... Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the V voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 162 32 ...

Page 163

... Maskable hardware CPU interrupts – Non-maskable software interrupt instruction (SWI) • Reset • Break interrupts MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 14.6.2 Stop Mode 14.3.2 Active Resets from Internal Sources SIM Counter 18.3.1.1 Normal Monitor Mode). for details. The SIM counter is ...

Page 164

... IAB DUMMY SP IDB DUMMY PC – 1[7:0] PC – 1[15:8] R/W MODULE INTERRUPT I BIT IAB SP – 4 IDB CCR R/W MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 164 shows interrupt recovery timing. SP – – – – Figure 14-8 Interrupt Entry Timing SP – – – 1 ...

Page 165

... CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See YES AS MANY INTERRUPTS AS EXIST ON CHIP MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 14-10. FROM RESET BREAK ...

Page 166

... The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. A software interrupt pushes PC onto the stack. A software interrupt does not push PC – hardware interrupt does. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 166 CLI LDA ...

Page 167

... I6–I1 — Interrupt Flags 1–6 These flags indicate the presence of interrupt requests from the sources shown Interrupt request present interrupt request present Bit 0 and Bit 1 — Always read 0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 14-3. Interrupt Sources Interrupt Source Reset ...

Page 168

... The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 168 6 ...

Page 169

... R/W Note: Previous data can be operand data or the WAIT opcode, depending on the last instruction. Figure 14-16 and Figure 14-17 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor WAIT ADDR + 1 SAME PREVIOUS DATA NEXT OPCODE Figure 14-15. Wait Mode Entry Timing show the timing for WAIT recovery. ...

Page 170

... The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery then used to time the recovery period. Figure 14-19 shows stop mode recovery time from interrupt. To minimize stop current, all pins configured as inputs should be driven MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 170 $6E0B $6E0C $00FF $00FE ...

Page 171

... Bit 7 Read: R Write: Reset Writing a 0 clears SBSW. Figure 14-20. Break Status Register (SBSR) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor STOP ADDR + 1 PREVIOUS DATA NEXT OPCODE Figure 14-18. Stop Mode Entry Timing STOP RECOVERY PERIOD STOP + 2 STOP + 2 Table 14-4 shows the mapping of these registers. ...

Page 172

... Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = POR or read of SRSR LVI — Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 172 PIN ...

Page 173

... This read/write bit enables software to clear status bits by accessing status registers while the MCU break state. To clear status bits during the break state, the BCFE bit must be set Status bits clearable during break 0 = Status bits not clearable during break MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 6 5 ...

Page 174

... System Integration Module (SIM) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 174 Freescale Semiconductor ...

Page 175

... If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. The following paragraphs describe the operation of the SPI module. Refer to of the SPI I/O registers. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-3 for a summary ...

Page 176

... SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device Figure 15-1. Block Diagram Highlighting SPI Block and Pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 176 INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT ...

Page 177

... SPI Status and Control $0011 Register (SPSCR) Write: See page 192. Reset: Read: SPI Data Register $0012 (SPDR) Write: See page 194. Reset: MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor INTERNAL BUS TRANSMIT DATA REGISTER SHIFT REGISTER RECEIVE DATA REGISTER ...

Page 178

... SPI module. After a byte enters the shift register of a slave SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 178 NOTE Figure 15-4 ...

Page 179

... The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 15 ...

Page 180

... SPI drives its MISO output only when its slave select input (SS) is low, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 180 15.6.2 Mode Fault ...

Page 181

... This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 1 ...

Page 182

... CLOCK WRITE TO SPDR BUS CLOCK WRITE TO SPDR BUS CLOCK Figure 15-8. Transmission Start Delay (Master) MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 182 INITIATION DELAY MSB 1 INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN SPSCK = BUS CLOCK ÷ 2; EARLIEST 2 POSSIBLE START POINTS LATEST SPSCK = BUS CLOCK ÷ 8; ...

Page 183

... For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. SPTE indicates when the next write can occur. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 3 ...

Page 184

... CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. 3 CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. 4 BYTE 2 SETS SPRF BIT. Figure 15-10. Missed Read of Overflow Condition MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 184 Figure 15-5 and Figure BYTE 2 BYTE ...

Page 185

... The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 15-11 illustrates this process ...

Page 186

... To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared. 15.7 Interrupts Four SPI status flags can be enabled to generate CPU interrupt requests. See MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 186 NOTE 15.4 Transmission ...

Page 187

... SPI transmitter empty (SPTE) — SPTE becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Table 15-1. SPI Interrupts ...

Page 188

... Chapter 14 System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write BCFE status bit is cleared during the break state, it remains cleared when the MCU exits the break state. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 188 15.7 Interrupts. ...

Page 189

... The serial clock synchronizes data transmission between master and slave devices master MCU, the SPSCK pin is the clock output slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 2 ...

Page 190

... See SPE SPMSTR (1 Don’t care MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 190 Figure 15-13. BYTE 1 BYTE 2 Figure 15-13. CPHA/SS Timing 15.12.2 SPI Status and Control Register. NOTE 15.6.2 Mode Fault Error.) Table 15-2. Table 15-2. SPI Configuration ...

Page 191

... SPWOM — SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor ...

Page 192

... This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 192 6 5 ...

Page 193

... In master mode, these read/write bits select one of four baud rates as shown in SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 15-3. SPI Master Baud Rate Selection SPR1 and SPR0 MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Baud Rate Divisor (BD) ...

Page 194

... Address: $0012 Bit 7 Read: R7 Write: T7 Reset: R7–R0/T7–T0 — Receive/Transmit Data Bits Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 194 Figure ...

Page 195

... TBR2–TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing the TACK bit. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor NOTE Figure ...

Page 196

... The timebase module can be used in this mode to generate a periodic wakeup from stop mode. If the internal clock generator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 196 ÷ 2 ÷ 2 ÷ ...

Page 197

... The TACK bit is a write-only bit and always reads as 0. Writing this bit clears TBIF, the timebase interrupt flag bit. Writing this bit has no effect Clear timebase interrupt flag effect MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor 6 5 ...

Page 198

... This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit Timebase is enabled Timebase is disabled and the counter initialized to 0s. MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 198 Freescale Semiconductor ...

Page 199

... TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 Freescale Semiconductor Figure 17 block diagram of the TIM. PRESCALER SELECT PS2 PS1 PS0 ELS0B ELS0A CH0F MS0A ...

Page 200

... SSA 1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device Figure 17-2. Block Diagram Highlighting TIM Block and Pins MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5 200 INTERNAL BUS PROGRAMMABLE TIMEBASE MODULE SINGLE BREAKPOINT ...