mc68hc05x4dw Freescale Semiconductor, Inc, mc68hc05x4dw Datasheet

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mc68hc05x4dw

Manufacturer Part Number
mc68hc05x4dw
Description
Xc68hc705x4 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor, Inc.
MC68HC05X4/D Rev 1.0
MC68HC05X4
MC68HC705X4
HCMOS Microcontroller Unit
TECHNICAL DATA
For More Information On This Product,
Go to: www.freescale.com

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mc68hc05x4dw Summary of contents

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... Freescale Semiconductor, Inc. MC68HC05X4 MC68HC705X4 HCMOS Microcontroller Unit For More Information On This Product, Go to: www.freescale.com MC68HC05X4/D Rev 1.0 TECHNICAL DATA ...

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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Modes of Operation and Pin Descriptions . . . . . . . . . . 13 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Resets, Interrupts and Low Power Modes . . . . . . . . . . . 49 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Parallel input/output ports . . . . . . . . . . . . . . . . . . . . . . . 65 Motorola CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . 111 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 127 Mechanical Dimensions and Ordering Information . 133 Glossary ...

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... Freescale Semiconductor, Inc. List of Sections MC68HC05X4 Rev 1.0 For More Information On This Product, List of Sections Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. Table of Contents Introduction Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mask options on the MC68HC05X4 . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Mask options on the MC68HC705X4 . . . . . . . . . . . . . . . . . . . . . . . . . 12 Modes of Operation Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 and Pin Descrip- Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 tions Single chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bootloader modes for the MC68HC05X4 and MC68HC705X4 . . . . . 15 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CPU Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Arithmetic/Logic Unit (ALU) ...

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... Freescale Semiconductor, Inc. Table of Contents Parallel input/output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 ports Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Port .66 Port .67 Port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Motorola CAN Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 TBF – Transmit buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 RBF – Receive buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Interface to the MC68HC05X4 CPU . . . . . . . . . . . . . . . . . . . . . . . . . .77 Interface to the MCAN bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Core Timer Contents ...

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... Freescale Semiconductor, Inc. Mechanical Dimen- Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sions and Ordering 28-pin SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Information Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Motorola SPS World Marketing World Wide Web Server . . . . . . . . 156 Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . . 156 ...

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... Freescale Semiconductor, Inc. Table of Contents MC68HC05X4 Rev 1.0 For More Information On This Product, Table of Contents Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mask options on the MC68HC05X4 . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Mask options on the MC68HC705X4 . . . . . . . . . . . . . . . . . . . . . . . . . 12 Mask option register (MOR Introduction The MC68HC05X4 with on-board controller area network (CAN) module is designed around the industry standard M68HC05 CPU core with its familiar and efficient instruction set. The Motorola CAN module (MCAN) ...

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... Freescale Semiconductor, Inc. Introduction Features • • • • • • • • • • • • • • MC68HC05X4 Rev 1.0 For More Information On This Product, Fully static design featuring the industry standard M68HC05 core On-chip oscillator with divide-by-2 or divide-by-10 option 4096 bytes of ROM (MC68HC05X4) ...

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... Freescale Semiconductor, Inc. OSC2 OSC1 VSS1 VDDH Line TX0 TX1 interface RX0 RX1 RESET MDS/TCAP(VPP) VDD VSS Figure 1. Functional block diagram Mask options on the MC68HC05X4 There are two mask options on the MC68HC05X4. These bits are programmed during manufacture and must be specified on the order form. • ...

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... Freescale Semiconductor, Inc. Introduction Mask options on the MC68HC705X4 The same options as for the MC68HC05X4 are available on the MC68HC705X4 device. These options must be programmed into the mask option register (MOR), at EPROM address $1F00, via the bootloader mode prior to operating the device in single chip mode. The MOR is latched in at reset in single chip mode to allow emulation of the masked ROM part ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single chip mode Bootloader modes for the MC68HC05X4 and MC68HC705X4 . . . . . 14 Bootloader Mode for the MC68HC05X4 . . . . . . . . . . . . . . . . . . . . . 14 Bootloader data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bootloader mode for the MC68HC705X4 . . . . . . . . . . . . . . . . . . . . 18 Pin descriptions VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MDS/TCAP(VPP OSC1/OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PA0– ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions Single chip mode This is the normal operating mode of the MC68HC05X4. In this mode the device functions as a self-contained microcomputer with all on-board peripherals, including the two 8-bit I/O ports available to the user. NOTE: For the MC68HC705X4 all vectors are fetched from EPROM (locations $1FF0– ...

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... Freescale Semiconductor, Inc. NOTE: ‘RAMST’ = the address of the first byte of RAM ‘BTROM’ = the address of the first byte of Bootloader ROM = $1F01 Note: • All resistors are 10 k unless otherwise specified • For 9600 baud operation, crystal should be 20 ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions Bootloader data Serial data byte format is 8 data bits, no parity, one stop bit. The baud format rate for both transmission and reception will be 9600 for a bus frequency ( 2MHz. OP Serial data packet format is: Program execution will automatically commence after the last byte is received ...

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... Freescale Semiconductor, Inc. Bootloader The program in bootloader ROM contains the following routines, which routines are accessed through a jump table at the start of the bootloader program (all routines end with an RTS instruction): Receive serial byte from user (address: BTROM + 3) This routine allows a serial byte to be read from PA0. The data read is written directly into memory, using the index register as an offset from the address of the first byte of RAM ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions PA3 = 1 ? Load Yes Read serial byte ‘COUNT’ Read next serial byte from PA0 into RAM Last byte ? Yes PC RAMST + 1? Execute user code in RAM Figure 2. MC68HC05X4 bootloader flowchart Bootloader mode This mode is used for programming the on-board EPROM and mask for the option register ...

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... Freescale Semiconductor, Inc. EPROM containing the user code are incremented independently it is essential that the data layout in the 2764 EPROM conforms exactly to the MC68HC705X4 memory map. The bootloader uses an external 12-bit counter with a clock and a reset function to address the memory device containing the code to be copied. ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions Bootloader The bootloader code deals with the copying of user code from an functions external EPROM into the on-chip EPROM. The bootloader function can only be used with an external EPROM. The bootloader performs a programming pass and then does a verify pass . ...

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... Freescale Semiconductor, Inc MDS/VPP 3 OSC1 20 MHz 4 OSC2 100 k 2 RESET 0 VSS PB2 PROG 23 PB1 390 VERF 28 PB6 390 22 PB0 MC68HC705X4 All resistors are 10 k unless otherwise specified Figure 4. MC68HC705X4 EPROM programming circuit 9-modes For More Information On This Product, ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions Bootloader PB2 = 0 ? Put RAMSUB in RAM PB3 = PB4 = 1 ? (Reserved) Set count to $0F00 Get byte from port A Program byte; JSR NXTADR End address ($1FFF) ? Verify Change instruction STA to EOR Increment count to $0F00; Start addr ¨ $0F00 A Figure 5 ...

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... Freescale Semiconductor, Inc. Pin descriptions PB7/TCMP RESET OSC1 OSC2 MDS/TCAP (VPP) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VSS VDD and VSS Power is supplied to the microcomputer via these two pins. VDD is the positive supply and VSS is ground the nature of CMOS designs that very fast signal transitions occur on the MCU pins ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions MDS/TCAP(VPP) During reset this pin is used as a mode select input (MDS) to determine the operating mode. It also serves as the input capture (TCAP) pin for the 16-bit programmable timer. In addition it is the EPROM programming voltage input pin (VPP) for the MC68HC705X4 device. ...

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... Freescale Semiconductor, Inc. Ceramic A ceramic resonator may be used instead of the crystal in cost-sensitive resonator applications. The circuit in ceramic resonator. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. This option is recommended only for applications that operate at an external clock frequency of 8MHz or less ...

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... Freescale Semiconductor, Inc. Modes of Operation and Pin Descriptions RESET This active low input pin is used to reset the MCU. Applying a logic zero to this pin forces the device to a known start-up state. An external RC-circuit can be connected to this pin to generate a power-on reset (POR) if required. In this case, the time constant must be great enough (minimum 100 ms) to allow the oscillator circuit to stabilise ...

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... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Arithmetic/Logic Unit (ALU Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Index Register Stack Pointer Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Condition Code Register Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Inherent Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Direct Extended Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Instruction Types Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Read-Modify-Write Instructions ...

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... Freescale Semiconductor, Inc. CPU Introduction This chapter describes the CPU registers and the HC05 instruction set. CPU Registers Figure 1 memory map PCH HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG CARRY/BORROW FLAG Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and non-arithmetic operations ...

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... Freescale Semiconductor, Inc. Bit 7 Reset: Index Register In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand. Bit 7 Reset: The 8-bit index register can also serve as a temporary data storage location. Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack ...

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... Freescale Semiconductor, Inc. CPU Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The two most significant bits of the program counter are ignored internally. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched ...

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... Freescale Semiconductor, Inc. interrupt vector interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state ...

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... Freescale Semiconductor, Inc. CPU Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU ...

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... Freescale Semiconductor, Inc. • • • Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long ...

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... Freescale Semiconductor, Inc. CPU Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. Indexed, 8-Bit Indexed, 8-bit offset instructions are 2-byte instructions that can access Offset data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode ...

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... Freescale Semiconductor, Inc. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. Instruction Types The MCU instructions fall into the following five categories: • ...

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... Freescale Semiconductor, Inc. CPU Read-Modify-Write These instructions read a memory location or a register, modify its Instructions contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. MC68HC05X4 For More Information On This Product, Table 1 ...

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... Freescale Semiconductor, Inc. Jump/Branch Jump instructions allow the CPU to interrupt the normal sequence of the Instructions program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met ...

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... Freescale Semiconductor, Inc. CPU Bit Manipulation The CPU can set or clear any writable bit in the first 256 bytes of Instructions memory, which includes I/O registers and on-chip RAM locations. The MC68HC05X4 For More Information On This Product, Table 3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear ...

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... Freescale Semiconductor, Inc. CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Control These instructions act on CPU registers and control CPU operation Instructions during program execution. 13-cpu For More Information On This Product, Table 4. Bit Manipulation Instructions ...

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... Freescale Semiconductor, Inc. CPU Instruction Set Summary Source Operation Form ADC # opr ADC opr ADC opr Add with Carry ADC opr ,X ADC opr ,X ADC ,X ADD # opr ADD opr ADD opr Add without Carry ADD opr ,X ADD opr ,X ADD ,X AND # opr AND opr ...

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... Freescale Semiconductor, Inc. Table 6. Instruction Set Summary (Continued) Source Operation Form BHS rel Branch if Higher or Same BIH rel Branch if IRQ Pin High BIL rel Branch if IRQ Pin Low BIT # opr BIT opr BIT opr Bit Test Accumulator with Memory Byte BIT opr ,X ...

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... Freescale Semiconductor, Inc. CPU Table 6. Instruction Set Summary (Continued) Source Operation Form CLI Clear Interrupt Mask CLR opr CLRA CLRX Clear Byte CLR opr ,X CLR ,X CMP # opr CMP opr CMP opr Compare Accumulator with Memory Byte CMP opr ,X CMP opr ,X CMP ,X ...

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... Freescale Semiconductor, Inc. Table 6. Instruction Set Summary (Continued) Source Operation Form JSR opr JSR opr JSR opr ,X Jump to Subroutine JSR opr ,X JSR ,X LDA # opr LDA opr LDA opr Load Accumulator with Memory Byte LDA opr ,X LDA opr ,X LDA ,X LDX # opr LDX opr ...

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... Freescale Semiconductor, Inc. CPU Table 6. Instruction Set Summary (Continued) Source Operation Form ROR opr RORA RORX Rotate Byte Right through Carry Bit ROR opr ,X ROR ,X RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC # opr SBC opr ...

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... Freescale Semiconductor, Inc. Table 6. Instruction Set Summary (Continued) Source Operation Form TST opr TSTA TSTX Test Memory Byte for Negative or Zero TST opr ,X TST ,X TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator C Carry/borrow flag CCR Condition code register ...

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... Freescale Semiconductor, Inc. CPU Specification MC68HC05X4 Rev 1.0 For More Information On This Product, CPU Go to: www.freescale.com 20-cpu ...

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... Freescale Semiconductor, Inc. Resets, Interrupts and Low Power Modes Contents Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Computer operating properly (COP) reset . . . . . . . . . . . . . . . . . . . 49 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Non-maskable software interrupt (SWI Maskable hardware interrupts MCAN interrupt (CIRQ Hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . . . . . 52 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 STOP ...

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... Freescale Semiconductor, Inc. Resets, Interrupts and Low Power Modes t VDDR V threshold (1-2V typical OXOV OSC1 t PORL Internal processor clock RESET (Internal power-on reset) Internal address bus 7FFE 7FFE Reset sequence Internal data bus Figure 1. Power-on reset and RESET Power-on reset A power-on reset occurs when a positive transition is detected on VDD ...

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... Freescale Semiconductor, Inc. RESET pin When the oscillator is running in a stable state, the MCU is reset when a logic zero is applied to the RESET input for a minimum period of 1.5 machine cycles (t part of its input to improve noise immunity. Illegal address When an opcode fetch occurs from an address which is not part of the reset RAM ($0050 – ...

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... Freescale Semiconductor, Inc. Resets, Interrupts and Low Power Modes RTI instruction (return from interrupt) causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete ...

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... Freescale Semiconductor, Inc. Maskable If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts hardware (internal and external) are masked. Clearing the I-bit allows interrupt interrupts processing to occur. NOTE: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared ...

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... Freescale Semiconductor, Inc. Resets, Interrupts and Low Power Modes WOI interrupt is bit 5 of the port configuration register ($03). This latch is set by the WOI, and is cleared by writing a zero to the bit. A WOI will cause the MPU to exit from STOP mode. Real time and There are two different core timer interrupt flags that cause a CTIMER ...

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... Freescale Semiconductor, Inc. WAIT: Low power modes STOP The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the internal oscillator is turned off (providing the MCAN is asleep, see including timer (and COP watchdog timer) operation. During the STOP mode, the core timer interrupt flags (CTOF and RTIF) ...

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... Freescale Semiconductor, Inc. Resets, Interrupts and Low Power Modes During the WAIT mode, the I-bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The Core Timer may be enabled to allow a periodic exit from the WAIT mode. See ...

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... Freescale Semiconductor, Inc. Reset Yes Is I-bit set? No CIRQ interrupt? No Core timer? No WOI interrupt? No 16-bit timer? No Fetch next instruction SWI instruction RTI instruction? No Execute instruction 9-resets For More Information On This Product, Yes Clear relevant IRQ request latch PC Yes Yes ...

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... Freescale Semiconductor, Inc. Resets, Interrupts and Low Power Modes STOP Stop oscillator and all clocks. Clear I bit. Reset No ? Yes No CIRQ/WOI ? Yes Turn on oscillator. Wait for time delay to stabilise (1) Fetch reset vector or (2) Service interrupt: a. stack b. set I-bit c. vector to interrupt routine Fetch instruction Figure 3 ...

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... Freescale Semiconductor, Inc. Contents Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Non-volatile memory (NVM MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 MCAN registers Memory map The MC68HC05X4 has an 8K byte memory map consisting of MCAN control registers, user ROM or EPROM , user RAM, bootloader ROM, and I/O (as illustrated in RAM The user RAM consists of 176 bytes of memory space shared with a 64 byte stack area ...

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... Freescale Semiconductor, Inc. Memory Non-volatile memory (NVM) The user NVM consists of 4096 bytes of ROM (MC68HC05X4) or EPROM (MC68HC705X4) from $0F00 to $1EFF and 16 bytes of user vectors from $1FF0 to $1FFF. The NVM has two modes of operation: single chip and bootloader (see Modes of Operation and Pin MC68HC05X4 Rev 1 ...

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... Freescale Semiconductor, Inc. MC68HC05X4 $0000 I/O (32 bytes) $0020 MCAN control registers (30 bytes) $003E $0050 RAM I $00C0 (176 bytes) Stack $0100 MC68HC705X4 $0F00 User ROM (4096 bytes) $1F00 $1F01 Bootloader ROM (239 bytes) SCI $1FF0–3 16-bit timer $1FF4–5 WOI $1FF6–7 Core timer $1FF8– ...

Page 60

... Freescale Semiconductor, Inc. Memory MCU registers Table 1. MC68HC05X4 and MC68HC705X4 register assignments Register Name Port A data/WOI enable (PADAT) Port B data (PBDAT) (Reserved) Port configuration (PCR) Port A DDR/ Pull-down enable (PADDDR) Port B DDR (PBDDR) (Reserved) Core timer control & status (CTCSR) ...

Page 61

... Freescale Semiconductor, Inc. MCAN registers Register name Address bit 7 Control (CCNTRL) Command (CCOM) Status (CSTAT) Interrupt (CINT) (1) Acceptance code (CACC) 1. Acceptance mask (CACM) 1. Bus timing 0 (CBT0) 1. Bus timing 1 (CBT1) 1. Output control (COCNTRL) (reserved) Transmit buffer identifier (TBI) RTR-bit, data length code ...

Page 62

... Freescale Semiconductor, Inc. Memory Register name Address bit 7 RTR-bit, data length code (RRTDL) Receive data segment 1 (RDS1) $0036 Receive data segment 2 (RDS2) $0037 Receive data segment 3 (RDS3) $0038 Receive data segment 4 (RDS4) $0039 Receive data segment 5 (RDS5) $003A Receive data segment 6 (RDS6) $003B ...

Page 63

... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Port Port Port registers Port A data register (PADR Port B data register (PBDR Port configuration register (PCR Port A data direction register (PADDR Port B data direction register (PBDDR Introduction In single chip mode there are 16 lines arranged as two 8-bit I/O ports. ...

Page 64

... Freescale Semiconductor, Inc. Parallel input/output ports Input/output programming Bi-directional port lines may be programmed as inputs or outputs under software control. The direction of each pin is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set ...

Page 65

... Freescale Semiconductor, Inc. WOI enable and pull-down enable registers control each pin individually; these registers are memory mapped to the same addresses as port A data register and data direction register (i.e $00 and $04). When the AWPS bit in the port configuration register (PCR) is set, port A WOI enable and pull-down enable registers are selected instead of port A data and DDR registers ...

Page 66

... Freescale Semiconductor, Inc. Parallel input/output ports Port registers The following sections explain in detail the individual bits in the data and control registers associated with the ports. Port A data Each bit can be configured as input or output via the corresponding data register (PADR) direction bit in the port A DDR. ...

Page 67

... Freescale Semiconductor, Inc. BPDE — Port B pull-down enable BWE — Port B WOI enable AWPS — Port A WOI and pull-down select Addresses $00 and $04 in the memory map are shared by two pairs of registers. The state of the AWPS bit determines which pair of registers are accessible at any time. When AWPS is clear the port A data register is found at $00, and the port A data direction register at $04 ...

Page 68

... Freescale Semiconductor, Inc. Parallel input/output ports MC68HC05X4 Rev 1.0 For More Information On This Product, Parallel input/output ports Go to: www.freescale.com 6-ports ...

Page 69

... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TBF – Transmit buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 RBF – Receive buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Interface to the MC68HC05X4 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . 75 MCAN control register (CCNTRL MCAN command register (CCOM MCAN status register (CSTAT MCAN interrupt register (CINT MCAN acceptance code register (CACC MCAN acceptance mask register (CACM MCAN bus timing register 0 (CBT0) ...

Page 70

... Freescale Semiconductor, Inc. Motorola CAN Introduction The MCAN includes all hardware modules necessary to implement the CAN transfer layer, which represents the kernel of the CAN bus protocol as defined by BOSCH GmbH, the originators of the CAN specification. For full details of the CAN protocol please refer to the published specifications ...

Page 71

... Freescale Semiconductor, Inc. Interface management logic Transmit buffer Receive buffer 0 Receive buffer 1 Microprocessor related logic 3-mcan For More Information On This Product, Bit timing logic Transceive logic Error management logic Bit stream processor Bus line related logic Figure 1. MCAN block diagram Motorola CAN Go to: www ...

Page 72

... Freescale Semiconductor, Inc. Motorola CAN Del Acknowledge Del frame of MC68HC05X4 For More Information On This Product, Ack CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR ID0 ID10 Start Figure 2. MCAN frame formats Motorola CAN Go to: www.freescale.com Del Ack Acknowledge Del CRC DLC0 ...

Page 73

... Freescale Semiconductor, Inc. Figure 2. MCAN frame formats (Continued) 5-mcan For More Information On This Product, frame of Start Motorola CAN Go to: www.freescale.com Motorola CAN Introduction MC68HC05X4 Rev 1.0 ...

Page 74

... Freescale Semiconductor, Inc. Motorola CAN TBF – Transmit buffer The transmit buffer is an interface between the CPU and the bit stream processor (BSP) and is able to store a complete message. The buffer is written by the CPU and read by the BSP. The CPU may access this buffer whenever transmit buffer access is set to released ...

Page 75

... Freescale Semiconductor, Inc. known, until after the first byte has been stored, whether or not the transmitting node will lose arbitration to another node. Interface to the MC68HC05X4 CPU The MCAN handles all the communication transactions flowing across the serial bus. For example, the CPU merely places a message to be transmitted into the transmit buffer and sets the TR bit ...

Page 76

... Freescale Semiconductor, Inc. Motorola CAN MCAN register blocks $0020 MCAN control registers 10 bytes $0029 $002A MCAN transmit buffer 10 bytes $0033 $0034 MCAN receive buffer 10 bytes $003D Figure 3. MCAN module memory map MC68HC05X4 For More Information On This Product, MCAN registers Acceptance code register ...

Page 77

... Freescale Semiconductor, Inc. MCAN control This register may be read or written to by the MCU; only the RR bit is register (CCNTRL) affected by the MCAN. Address: External Reset: Reset: with RR bit set NOTE: Only the RR bit in this register can be written when the RR bit is set. MODE — Undefined mode This bit must never be set by the CPU as this would result in the transmit and receive buffers being mapped out of memory ...

Page 78

... Freescale Semiconductor, Inc. Motorola CAN NOTE: When setting TIE while TCS or TBA is set, no interrupt will be requested. Successful transmission must occur after setting the TIE bit to get an interrupt flag. RIE — Receive interrupt enable 1 = Enabled – The CPU will get an interrupt request whenever Disabled – ...

Page 79

... Freescale Semiconductor, Inc. MCAN command This is a write only register; a read of this location will always return register (CCOM) the value $FF. This register may be written only when the RR bit in CCNTRL is clear. Do not use read-modify-write instructions on this register (e.g. BSET, BCLR). Address: External Reset: Reset: with RR bit set RX0 — ...

Page 80

... Freescale Semiconductor, Inc. Motorola CAN SLEEP — sleep When the SLEEP bit is set during a non synchronous state, an immediate wake-up wil be generated by the MCAN module. (See RR bit description for more details Sleep – The MCAN will go into sleep mode, as long as there Wake-up – ...

Page 81

... Freescale Semiconductor, Inc. RRB — Release receive buffer When set this releases the receive buffer currently attached to the CPU, allowing the buffer to be reused by the MCAN. This may result in another message being received, which could cause another receive interrupt request (if RIE is set). This bit is cleared automatically when a message is received, i ...

Page 82

... Freescale Semiconductor, Inc. Motorola CAN MCAN status This is a read only register; only the MCAN can change its contents. register (CSTAT) Address: External Reset: Reset: with RR bit set BS — Bus status This bit is set (off-bus) by the MCAN when the transmit error counter reaches 256 ...

Page 83

... Freescale Semiconductor, Inc. TCS — Transmission complete status This bit is cleared by the MCAN when TR becomes set. When TCS is set it indicates that the last requested transmission was successfully completed. If, after TCS is cleared, but before transmission begins, an abort transmission command is issued then the transmit buffer will be released and TCS will remain clear ...

Page 84

... Freescale Semiconductor, Inc. Motorola CAN RBS — Receive buffer status This bit is set by the MCAN when a new message is available. When clear this indicates that no message has become available since the last RRB command. The bit is cleared when RRB is set. However, if the second receive buffer already contains a message, then control of that buffer is given to the CPU and RBS is immediately set again ...

Page 85

... Freescale Semiconductor, Inc. OIF — Overrun interrupt flag When OIE is set then this bit will be set when a data overrun condition is detected. Like all the bits in this register, OIF is cleared by reading the register, or when reset request is set. EIF — Error interrupt flag When EIE is set then this bit will be set by a change in the error or bus status bits in the MCAN status register ...

Page 86

... Freescale Semiconductor, Inc. Motorola CAN MCAN On reception each message is written into the current receive buffer. acceptance code The MCU is only signalled to read the message however passes the register (CACC) criteria in the acceptance code and acceptance mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped) ...

Page 87

... Freescale Semiconductor, Inc. MCAN The acceptance mask register specifies which of the corresponding bits acceptance mask in the acceptance code register are relevant for acceptance filtering. register (CACM) NOTE: This register can be accessed only when the RR bit in CCNTRL is set. Address: Reset: AM0 – AM7 — Acceptance mask bits ...

Page 88

... Freescale Semiconductor, Inc. Motorola CAN MCAN bus timing register 0 (CBT0) Address: Reset: NOTE: This register can be accessed only when the RR bit in CCNTRL is set. SJW1, SJW0 — Synchronization jump width bits The synchronization jump width defines the maximum number of system clock (t lengthened, to achieve resynchronization on data transitions on the bus (see BRP5 – ...

Page 89

... Freescale Semiconductor, Inc. f osc Divide by OSC1 2 Divide Figure 11. Oscillator block diagram MCAN bus timing This register can only be accessed only when the RR bit in CCNTRL is register 1 (CBT1) set. Address: Reset: SAMP — Sampling This bit determines the number of samples of the serial bus to be taken per bit time ...

Page 90

... Freescale Semiconductor, Inc. Motorola CAN SYNC_SEG 1 clock cycle Transmit point Figure 13. Segments within the bit time SYNC_SEG this period. Transmit point A node in transmit mode will transfer a new value to the MCAN bus at this point. Sample point If the three samples per bit option is selected then this point marks the position of the third sample ...

Page 91

... Freescale Semiconductor, Inc. Calculation of the bit time NOTE: TSEG2 must be at least 2 t 000. (If three samples per bit mode is selected then TSEG2 must be at least 3 t TSEG1 must be at least as long as TSEG2. The synchronization jump width (SJW) may not exceed TSEG2, and must be at least t propagation delays ...

Page 92

... Freescale Semiconductor, Inc. Motorola CAN MCAN output This register allows the setup of different output driver configurations control register under software control. The user may select active pull-up, pull-down, (COCNTRL) float or push-pull output. NOTE: This register can be accessed only when the RR bit in CCNTRL is set. ...

Page 93

... Freescale Semiconductor, Inc. Biphase mode If the CAN modules are isolated from the bus lines by a transformer then the bit stream has to be coded so that there is no resulting dc component. There is a flip-flop within the MCAN that keeps the last dominant configuration; its direct output goes to TX0 and its complement to TX1. The flip-flop is toggled for each dominant bit ...

Page 94

... Freescale Semiconductor, Inc. Motorola CAN The actions of these bits in the output control register are as shown in Table Table 5. MCAN driver output levels Mode TD OCPOLi OCTPi 0 1 Float Pull-down Pull- Push-pull 0 1 Transmit buffer identifier register (TBI) ...

Page 95

... Freescale Semiconductor, Inc. Remote transmission request and data length code register (TRTDL) Address: Reset: Figure 16. RTR and Data Length Code Register (TRTDL) ID2 – ID0 — Identifier bits These bits contain the least significant bits of the transmit buffer identifier. RTR — Remote transmission request DLC3 – ...

Page 96

... Freescale Semiconductor, Inc. Motorola CAN Transmit data segment registers (TDS) 1 – 8 Address: Reset: DB7 – DB0 — data bits These data bits in the eight data segment registers make up the bytes of data to be transmitted. The number of bytes to be transmitted is determined by the data length code. ...

Page 97

... Freescale Semiconductor, Inc. Remote The layout of this register is identical to the TRTDL register (see transmission transmission request and data length code register request and data Address: length code register (RRTDL) Reset: Figure 19. RTR and Data Length Code Register (RRTDL) Receive data The layout of these registers is identical to the TDSx registers (see segment registers Transmit data segment registers (TDS) 1 – ...

Page 98

... Freescale Semiconductor, Inc. Motorola CAN Interface to the MCAN bus Physically, the MCAN bus may be composed of two wires. The bus can take on one of two values: dominant or recessive. During simultaneous transmission of dominant and recessive bits by two or more CAN modules the resulting bus value will be dominant. (For example, with a wired-AND implementation of the bus, the dominant level would correspond to a logic 0, and the recessive level to a logic 1 ...

Page 99

... Freescale Semiconductor, Inc. Termination network 1.75V 3.25V TX0 680 TX1 680 150k RX0 150k RX1 2 x 30k CANL CANH VDDH MCAN bus lines Figure 21. A typical physical interface between the MCAN and the MCAN bus lines 31-mcan For More Information On This Product, ...

Page 100

... Freescale Semiconductor, Inc. Motorola CAN Single wire In the event of a bus fault occurring, limited operation of the MCAN bus operation may still be possible, depending on the nature of the fault. If the fault is due to a short circuit between the two bus lines or between one of the ...

Page 101

... Freescale Semiconductor, Inc. Port configuration register (PCR) Address: Reset: CAF — MCAN asleep flag In order to minimize power consumption, the active comparator is switched off and the sleep comparator circuitry is used to detect activity on the bus. When in sleep mode the MCAN stops its own clocks, leaving the MCU in normal run mode ...

Page 102

... Freescale Semiconductor, Inc. Motorola CAN MC68HC05X4 For More Information On This Product, Motorola CAN Go to: www.freescale.com 34-mcan ...

Page 103

... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Real time interrupts (RTI 105 Computer operating properly (COP) watchdog timer . . . . . . . . . . . . 105 Core timer registers 106 Core timer control and status register (CTCSR 106 Core timer counter register (CTCR 108 Core timer during WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Core timer during STOP ...

Page 104

... Freescale Semiconductor, Inc. Core Timer Overflow detect circuit (Core timer control & status) CTOF RTIF CTOE RTIE 8 Interrupt circuit To interrupt logic Figure 1. Core timer block diagram flags, are located in the CTIMER control and status register (CTCSR) at location $08. ...

Page 105

... Freescale Semiconductor, Inc. When CTOE (core timer overflow enable) is set, a CPU interrupt request is generated when the CTOF bit is set. Reset clears CTOE. The core timer counter register (CTCR read-only register that contains the current value of the 8-bit ripple counter at the beginning of the timer chain ...

Page 106

... Freescale Semiconductor, Inc. Core Timer If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. COP timeout is prevented by writing a ‘0’ to bit 0 of address $1FF0. When the COP is cleared, only the final divide-by-eight stage is cleared (see The COP function is a mask option, enabled or disabled during device manufacture ...

Page 107

... Freescale Semiconductor, Inc. This bit is set when the output of the chosen stage becomes active; an interrupt request will be generated if RTIE is set. When set, the bit may be cleared by writing a ‘0’ to it. CTOE — Core timer overflow interrupt enable RTIE — Real time interrupt enable RT1, RT0 — ...

Page 108

... Freescale Semiconductor, Inc. Core Timer Core timer counter register (CTCR) Address: Reset: The core timer counter register is a read-only register, which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. Reset clears this register. Core timer during WAIT The CPU clock halts during the WAIT mode, but the core timer remains active ...

Page 109

... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Port configuration register (PCR 110 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Timer control register (TCR 114 Timer status register (TSR 116 Input capture function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Output compare function 119 Output compare registers ...

Page 110

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contain the high and low byte of that functional segment. Accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed ...

Page 111

... Freescale Semiconductor, Inc. Internal processor clock High Low byte byte $16 Output ( 4 ) compare register $17 Output compare circuit $13 TSR ICF OCF TOF (Timer status register) ICIE Interrupt circuit Table 1. 16-bit programmable timer block diagram 3-ptimer For More Information On This Product, Internal bus 8-bit ...

Page 112

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer Counter The key element in the programmable timer is a 16-bit, free-running counter, or counter register, preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the timer a resolution the internal bus clock is 2MHz. The counter is incremented during the low portion of the internal bus clock ...

Page 113

... Freescale Semiconductor, Inc. Address: Reset: Address: Reset: The double-byte, free-running counter can be read from either of two locations, $18 – $19 (counter register) or $1A – $1B (alternate counter register). A read from only the less significant byte (LSB) of the free-running counter ($19 or $1B) receives the count value at the time of the read ...

Page 114

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer prescaler, the value in the free-running counter repeats every 262144 internal bus clock cycles. TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set. Bits 8 – 15 — MSB of counter/alternate counter register ...

Page 115

... Freescale Semiconductor, Inc. ICIE — Input capture interrupt enable If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag in the timer status register (TSR) is set. OCIE — Output compare interrupt enable If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag in TSR is set. TOIE — ...

Page 116

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer Timer status The timer status register ($13) contains the status bits for the interrupt register (TSR) conditions ICF, OCF, and TOF. Accessing the timer status register satisfies the first condition required to clear the status bits. The remaining step is to access the register corresponding to the status bit ...

Page 117

... Freescale Semiconductor, Inc. When using the timer overflow function and reading the free-running counter at random times to measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally cleared if: 1. the timer status register is read or written when TOF is set, and 2. the LSB of the free-running counter is read, but not for the purpose Reading the alternate counter register instead of the counter register will avoid this potential problem ...

Page 118

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer bit (IEDG). The most significant 8 bits are stored in the input capture high register at $14, the least significant in the input capture low register at $15. The result obtained from an input capture will be one greater than the value of the free-running counter on the rising edge of the internal bus clock preceding the external transition ...

Page 119

... Freescale Semiconductor, Inc. Output compare ‘Output compare’ technique that may be used, for example, to function generate an output waveform signal when a specific time period has elapsed, by presetting the output compare register to the appropriate value. Output compare registers Address: Reset: Address: ...

Page 120

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer location $17 will not inhibit the compare function. The processor can write to either byte of the output compare register without affecting the other byte. The output level (OLVL) bit is clocked to the output level register whether the output compare flag (OCF) is set or clear. The minimum time required to update the output compare register is a function of the program rather than the internal hardware ...

Page 121

... Freescale Semiconductor, Inc. occurred during the STOP period. If the device is reset to exit STOP mode, then no input capture flag or data remains, even if a valid input capture edge occurred. Timer state diagrams The relationships between the internal clock signals, the counter contents and the status of the flag bits are shown in the following diagrams. It should be noted that the signals labelled ‘ ...

Page 122

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer Internal processor clock T00 T01 Internal timer clocks T10 T11 16-bit counter Input edge Internal capture latch Input capture register Input capture flag Note: If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then the input capture fl ...

Page 123

... Freescale Semiconductor, Inc. Internal processor clock T00 T01 Internal timer clocks T10 T11 16-bit counter Output compare CPU writes $F457 register Compare register latch Output compare flag and TCMP Note: (1) The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state T01 ...

Page 124

... Freescale Semiconductor, Inc. 16-Bit Programmable Timer MC68HC05X4 Rev 1.0 For More Information On This Product, 16-Bit Programmable Timer Go to: www.freescale.com 16-ptimer ...

Page 125

... Freescale Semiconductor, Inc. Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Maximum ratings 126 Thermal characteristics and power considerations . . . . . . . . . . . . . . 126 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Introduction This section contains the electrical specifications and associated timing information for the MC68HC05X4 and MC68HC705X4 . NOTE: Because the MC68HC705X4 has not yet been characterised fully the information and values given for this device are for guidance only ...

Page 126

... Freescale Semiconductor, Inc. Electrical Characteristics Maximum ratings Rating (1) Supply voltage Input Voltage: (Ports, OSC1, RESET, RX0/1) Input Voltage: (MDS/TCAP – MC68HC05X4) Input Voltage: (VPP – MC68HC705X4) Operating temperature range (standard plastic package) Storage temperature range (2) Current drain per pin – excluding VDD and VSS 1 ...

Page 127

... Freescale Semiconductor, Inc. where INT P I/O An approximate relationship between P Solving equations [1] and [2] for K gives: where constant for a particular part. K can be determined by measuring P values of P above equations. The package thermal characteristics are shown in Table 3-elec For More Information On This Product, ...

Page 128

... Freescale Semiconductor, Inc. Electrical Characteristics DC electrical characteristics Table 2. DC electrical characteristics ( Characteristic Output voltage I = –10 A LOAD I = +10 A LOAD Output high voltage (I = 0.8 mA) LOAD Ports Output low voltage (I = +1.6 mA) LOAD Ports Input high voltage Ports, OSC1, MDS, RESET Input low voltage ...

Page 129

... Freescale Semiconductor, Inc. 3. Run (Operating Wait I : Measured using external square wave clock source ( rail loads, less than 50pF on all outputs OSC2 5pF on XOSC2. Wait, Stop I figured as inputs 0 OSC2 capacitance. 4. EPROM data is preliminary and cannot be guaranteed. ...

Page 130

... Freescale Semiconductor, Inc. Electrical Characteristics AC electrical characteristics Table 5. AC electrical characteristics (V DD Characteristic Frequency of operation Oscillator frequency MCAN module bus frequency MCU bus frequency Processor cycle time MCAN module cycle time Oscillator clock pulse width WOI pulse width RESET pulse width ...

Page 131

... Freescale Semiconductor, Inc. Mechanical Dimensions and Ordering Information Contents 28-pin SOIC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Verification media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 MC order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 1-mech Mechanical Dimensions and Ordering Information For More Information On This Product, Go to: www.freescale.com General Description MC68HC05X4 Rev 1.0 ...

Page 132

... Freescale Semiconductor, Inc. Mechanical Dimensions and Ordering Information 28-pin SOIC package – A – Case 751F- 0.25 T Dim. Min. Max. A 17.80 18.05 1.Dimensions ‘A’ and ‘B’ are datums and ‘T’ datum B 7.40 7.60 surface. C 2.35 2.65 2.Dimensioning and tolerancing per ANSI Y14.5M, 1982. ...

Page 133

... For More Information On This Product, Mechanical Dimensions and Ordering Information Package type Temperature 28-pin SOIC 0 to +70 C 28-pin SOIC –40 to +85 C MC68HC05X4CDW 28-pin SOIC 0 to +70 C 28-pin SOIC –40 to +85 C MC68HC705X4CDW Go to: www.freescale.com Ordering information Part number MC68HC05X4DW MC68HC705X4DW MC68HC05X4 Rev 1.0 ...

Page 134

... Freescale Semiconductor, Inc. Mechanical Dimensions and Ordering Information MC68HC05X4 Rev 1.0 Mechanical Dimensions and Ordering Information For More Information On This Product, Go to: www.freescale.com 4-mech ...

Page 135

... Freescale Semiconductor, Inc. A — See “accumulator (A).” accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode — A mode of PLL operation during startup before the PLL locks on a frequency. Also see "tracking mode." ...

Page 136

... Freescale Semiconductor, Inc. Glossary bit — A binary digit. A bit has a value of either logic 0 or logic 1. branch instruction — An instruction that causes the CPU to continue processing at a memory location other than the next sequential address. break module — A module in the M68HC08 Family. The break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint — ...

Page 137

... Freescale Semiconductor, Inc. clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a base clock signal from which the system clocks are derived. The CGM may include a crystal oscillator circuit and or phase-locked loop (PLL) circuit. comparator — A device that compares the magnitude of two inputs. A digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (COP) — ...

Page 138

... Freescale Semiconductor, Inc. Glossary CPU registers — Memory locations that are wired directly into the CPU logic instead of being part of the addressable memory map. The CPU always has direct access to the information in these registers. The CPU registers in an M68HC08 are: • ...

Page 139

... Freescale Semiconductor, Inc. external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch — To copy data from a memory location into the accumulator. firmware — Instructions and data programmed into nonvolatile memory. ...

Page 140

... Freescale Semiconductor, Inc. Glossary instructions — Operations that a CPU can perform. Instructions are expressed by programmers as assembly language mnemonics. A CPU interprets an opcode and its associated operand(s) and instruction. interrupt — A temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. ...

Page 141

... Freescale Semiconductor, Inc. mask option — A optional microcontroller feature that the customer chooses to enable or disable. mask option register (MOR) — An EPROM location containing bits that enable or disable certain MCU features. MCU — Microcontroller unit. See “microcontroller.” memory location — Each M68HC08 memory location holds one byte of data and has a unique address ...

Page 142

... Freescale Semiconductor, Inc. Glossary opcode — A binary code that instructs the CPU to perform an operation. open-drain — An output that has no pullup transistor. An external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand — Data on which an operation is performed. Usually a statement consists of an operator and an operand ...

Page 143

... Freescale Semiconductor, Inc. port — A set of wires for communicating with off-chip devices. prescaler — A circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program — A set of computer instructions that cause a computer to perform a desired operation or operations. ...

Page 144

... Freescale Semiconductor, Inc. Glossary ROM — Read-only memory. A type of memory that can be read but cannot be changed (written). The contents of ROM must be specified before manufacturing the MCU. SCI — See "serial communication interface module (SCI)." serial — Pertaining to sequential transmission over a single line. ...

Page 145

... Freescale Semiconductor, Inc. subroutine — A sequence of instructions to be used more than once in the course of a program. The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the flow of the main program to execute the instructions in the subroutine ...

Page 146

... Freescale Semiconductor, Inc. Glossary vector — A memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a frequency that is controlled voltage applied to a control input. waveform — A graphical representation in which the amplitude of a wave is plotted against time. ...

Page 147

... Freescale Semiconductor, Inc. Numerics 28-pin SOIC mechanical dimensions . . . . . . . . . . . .134 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .24 A AC7-AC0 bits in CACC . . . . . . . . . . . . . . . .88 accumulator .30 addressing modes . . . . . . . . . . . . . . . . . . . .34 ALU — arithmetic/logic unit . . . . . . . . . . . . .34 AM0–AM7 bits in CACM . . . . . . . . . . . . . . .89 AT bit in CCOM . . . . . . . . . . . . . . . . . . . . . .83 AWPS bit in PCR .69 B biphase mode . . . . . . . . . . . . . . . . . . . . . . .95 bit manipulation instructions . . . . . . . . . . . .40 bit time calculation .93 block diagrams core timer ...

Page 148

... Freescale Semiconductor, Inc. Index RIF – receive interrupt flag .87 TIF – transmit interrupt flag WIF – wake-up interrupt flag clocks ceramic resonator . . . . . . . . . . . . . . . . .26 crystal .25 external . . . . . . . . . . . . . . . . . . . . . . . . .26 OSC1/OSC2 . . . . . . . . . . . . . . . . . . . . .25 oscillator connections . . . . . . . . . . . . . . .26 COCNTRL — MCAN output control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 OCM1, OCM0 – output control mode bits . . . . . . . . . . . . . . . . . . . . . . . . . .94 COMPSEL bit in CCOM ...

Page 149

... Freescale Semiconductor, Inc. hardware interrupts . . . . . . . . . . . . . . . . . . .53 H-bit in CCR . . . . . . . . . . . . . . . . . . . . . . . .32 I I/O ports PA0–PA7/PB0–PB7 .27 pin functions .67 programming . . . . . . . . . . . . . . . . . . . . .66 structure . . . . . . . . . . . . . . . . . . . . . . . . .66 ICF-bit in TSR . . . . . . . . . . . . . . . . . . . . . .118 ICH/ICL — input capture registers ICIE-bit in TCR . . . . . . . . . . . . . . . . . . . . .117 ID10–ID3 bits in TBI . . . . . . . . . . . . . . . . . .96 ID2–ID0 bits in TRTDL . . . . . . . . . . . . . . . .97 IEDG-bit in TCR . . . . . . . . . . . . . . . . . . . .117 illegal address reset ...

Page 150

... Freescale Semiconductor, Inc. Index N N-bit in CCR . . . . . . . . . . . . . . . . . . . . . . . .33 negative flag . . . . . . . . . . . . . . . . . . . . . . . .33 non-volatile memory (NVM .60 normal mode .95 normal mode .95 O OCF-bit in TSR . . . . . . . . . . . . . . . . . . . . .118 OCH/OCL — output compare OCIE-bit in TCR . . . . . . . . . . . . . . . . . . . .117 OCM1, OCM0 bits in COCNTRL .94 OIE bit in CCNTRL . . . . . . . . . . . . . . . . . . .79 OIF bit in CINT . . . . . . . . . . . . . . . . . . . . . .87 OLVL-bit in TCR . . . . . . . . . . . . . . . . . . . .117 opcode map ...

Page 151

... Freescale Semiconductor, Inc. RBI — receive buffer identifier register RBS bit in CSTAT . . . . . . . . . . . . . . . . . . . .86 RCTOF bit in CTCSR . . . . . . . . . . . . . . . .109 RDS — receive data segment registers read-modify-write instructions real time interrupt (RTI .107 rate selection . . . . . . . . . . . . . . . . . . . .109 register outline MCAN . . . . . . . . . . . . . . . . . . . . . . . . . .63 register/memory instructions . . . . . . . . . . . .37 relative addressing mode . . . . . . . . . . . . . .36 RESET ...

Page 152

... Freescale Semiconductor, Inc. Index VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 VSS and VDD . . . . . . . . . . . . . . . . . . . . . . .24 VSS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 W WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 watchdog — see COP .51 Web server . . . . . . . . . . . . . . . . . . . . . . . .156 Web site . . . . . . . . . . . . . . . . . . . . . . . . . .156 WIF bit in CINT . . . . . . . . . . . . . . . . . . . . . .86 wired-OR interrupt . . . . . . . . . . . . . . . . . . . .53 WOI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 WOIF bit in PCR . . . . . . . . . . . . . . . . . . . . .68 Z Z-bit in CCR .33 zero flag .33 MC68HC05X4 Rev 1.0 For More Information On This Product, Index Go to: www ...

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... Freescale Semiconductor, Inc. This document contains the latest data available at publication time. For updates, contact one of the centers listed below: Literature Distribution Centers Order literature by mail or phone. USA/Europe Motorola Literature Distribution P.O. Box 5405 Denver, Colorado, 80217 Phone 1-303-675-2140 US & Canada only http://sps ...

Page 154

... Freescale Semiconductor, Inc. Literature Updates Hong Kong Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong Phone 852-26629298 Customer Focus Center 1-800-521-6274 Mfax To access this worldwide faxing service call or contact by electronic mail or the internet: RMFAX0@email.sps.mot.com TOUCH-TONE 1-602-244-6609 http://sps ...

Page 155

... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

Page 156

... Fax: 303-675-2150 5 LDCForFreescaleSemiconductor @hibbertgroup.com Freescale Semiconductor, Inc. RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program http://www ...

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