mc68hc11d0cfn2 Freescale Semiconductor, Inc, mc68hc11d0cfn2 Datasheet

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mc68hc11d0cfn2

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mc68hc11d0cfn2
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M68hc11 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Freescale Semiconductor, Inc.
MC68HC711D3
MC68HC11D3
MC68HC11D0
MC68L11D0
Data Sheet
M68HC11
Microcontrollers
MC68HC711D3/D
Rev. 2
9/2003
MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product,
Go to: www.freescale.com

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mc68hc11d0cfn2 Summary of contents

Page 1

... Freescale Semiconductor, Inc. M68HC11 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS For More Information On This Product, Go to: www.freescale.com MC68HC711D3 MC68HC11D3 MC68HC11D0 MC68L11D0 Data Sheet MC68HC711D3/D Rev. 2 9/2003 ...

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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. MC68HC711D3 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document ...

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... Freescale Semiconductor, Inc. Revision History Revision Date Level Reformatted to curent publications standards Removed references to PROG mode. Corrected pin assignments for: Figure 1-2. Pin Assignments for 40-Pin Plastic DIP Figure 1-3. Pin Assignments for 44-Pin PLCC Added September, 1.9 Interrupt Request (IRQ) 2 2003 2.4 Programmable Read-Only Memory (PROM) data ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Section 2. Operating Modes and Memory . . . . . . . . . . . . . . . . . . . . . . 21 Section 3. Central Processor Unit (CPU Section 4. Resets, Interrupts, and Low-Power Modes . . . . . . . . . . . . 51 Section 5. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Section 6. Serial Communications Interface (SCI Section 7. Serial Peripheral Interface (SPI Section 8. Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Section 9 ...

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... Freescale Semiconductor, Inc. List of Sections Data Sheet 6 For More Information On This Product, List of Sections Go to: www.freescale.com MC68HC711D3 — Rev. 2 MOTOROLA ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.5 Power Supply (V 1.6 Reset (RESET 1.7 Crystal Driver and External Clock Input (XTAL and EXTAL 1.8 E-Clock Output ( 1.9 Interrupt Request (IRQ 1.10 Non-Maskable Interrupt/Programming Voltage (XIRQ/V 1.11 MODA and MODB (MODA/LIR and MODB/V 1 ...

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... Freescale Semiconductor, Inc. Table of Contents 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.6.1 3.2.6.2 3.2.6.3 3.2.6.4 3.2.6.5 3.2.6.6 3.2.6.7 3.2.6.8 3.3 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.6 Instruction Set 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Data Sheet 8 For More Information On This Product, Section 3. Central Processor Unit (CPU) Accumulators A, B, and Index Register X (IX Index Register Y (IY Stack Pointer (SP) ...

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... Freescale Semiconductor, Inc. 4.4 Low-Power Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.4.1 4.4.2 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.2 Port 5.3 Port 5.3.1 5.3.2 5.4 Port 5.4.1 5.4.2 5.4.3 5.5 Port 5.5.1 5.5.2 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.3 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5 Wakeup Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.5.1 6.5.2 6.6 SCI Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.7 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.8 Status Flags and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3 SPI Transfer Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7.4 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 MC68HC711D3 — ...

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... Freescale Semiconductor, Inc. Table of Contents 7.5 SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.5.1 7.5.2 7.5.3 7.5.4 7.6 SPI System Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.7 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.7.1 7.7.2 7.7.3 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8.2 Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.3 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.3.1 8.3.2 8.3.3 8.4 Output Compare (OC 102 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.4.6 8.4.7 8.4.8 8.4.9 8.4.10 8.5 Real-Time Interrupt 110 8.5.1 8.5.2 8.5.3 8.6 Computer Operating Properly Watchdog Function 113 8.7 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.7.1 8.7.2 8.7.3 Data Sheet 10 For More Information On This Product, Master In/Slave Out (MISO Master Out/Slave In (MOSI) ...

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... Freescale Semiconductor, Inc. 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 9.3 Functional Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . 118 9.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.6 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.7 Peripheral Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9.8 Expansion Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.9 Serial Peripheral Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Section 10. Ordering Information and Mechanical Specifications 10 ...

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... Freescale Semiconductor, Inc. Table of Contents Data Sheet 12 For More Information On This Product, Table of Contents Go to: www.freescale.com MC68HC711D3 — Rev. 2 MOTOROLA ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 1.1 Introduction This section depicts the general characteristics and features of the MC68HC711D3 high-density complementary metal-oxide semiconductor (HCMOS) microcontroller unit (MCU). The MC68HC711D3 contains highly sophisticated on-chip peripheral functions. This high-speed, low-power programmable read-only memory (PROM) MCU has a nominal bus speed of 3 MHz ...

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... Freescale Semiconductor, Inc. General Description • Available in these packages: – – – 1.3 Structure Refer to Figure MODA/LIR RESET MODB/V STBY MODE CONTROL PA7 PA6 PA5 PA4 PORT A PA3 PA2 PA1 PA0 MULTIPLEXED ADDRESS/DATA BUS DATA DIRECTION REGISTER B PORT B Figure 1-1. MC68HC711D3 Block Diagram ...

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... Freescale Semiconductor, Inc. 1.4 Pin Descriptions Refer to Figure MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product, 1-2, Figure 1-3, and Figure 1 PC0 2 PC1 3 PC2 4 PC3 5 PC4 6 PC5 7 PC6 8 PC7 9 XIRQ PD7/R/W 11 PD6/AS 12 RESET 13 IRQ 14 PD0 15 PD1 16 PD2 17 PD3 18 PD4 19 PD5 20 Figure 1-2. Pin Assignments for 40-Pin Plastic DIP ...

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... Freescale Semiconductor, Inc. General Description 1.5 Power Supply ( Power is supplied to the MCU through V (+5 V ±10%) and V QFP additional ground pin. 1.6 Reset (RESET) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or computer operating properly (COP) watchdog circuit ...

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... Freescale Semiconductor, Inc. 1.7 Crystal Driver and External Clock Input (XTAL and EXTAL) These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. The frequency applied to these pins is four times higher than the desired E-clock rate. Refer to for crystal and clock connections ...

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... Freescale Semiconductor, Inc. General Description 1.8 E-Clock Output ( the output connection for the internally generated E clock. The signal from E is used as a timing reference. The frequency of the E-clock output is one fourth that of the input frequency at the XTAL and EXTAL pins. The E clock can be turned off in single-chip mode for greater noise immunity if desired ...

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... Freescale Semiconductor, Inc. 1.12 Read/Write (R/W) This pin performs either of two separate functions, depending on the operating mode. • In single-chip and bootstrap modes, R/W functions as input/output port D bit 7. Refer to • In expanded multiplexed and test modes, R/W performs a read/write function. R/W controls the direction of transfers on the external data bus. ...

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... Freescale Semiconductor, Inc. General Description Port/Bit 1. In the 40-pin package, pins PA4 and PA6 are not bonded. Their associated I/O and output compare functions are not available externally. They can still be used as internal software timers, however. Data Sheet 20 For More Information On This Product, Table 1-1 ...

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... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 2.1 Introduction This section contains information about: • The modes that define MC68HC711D3 operating conditions • The on-chip memory that allows the microcontroller unit (MCU configured for various applications • The 4-Kbytes of programmable read-only memory (PROM) 2 ...

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... Freescale Semiconductor, Inc. Operating Modes and Memory 2.2.2 Expanded Multiplexed Mode In the expanded-multiplexed mode, the MCU can address Kbytes of address space. High-order address bits are output on the port B pins. Low-order address bits and the bidirectional data bus are multiplexed on port C. The AS pin provides the control output used in demultiplexing the low-order address ...

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... Freescale Semiconductor, Inc. 2.2.4 Special Test Mode This special expanded mode is primarily intended or production testing. The user can access a number of special test control bits in this mode. Reset and interrupt vectors are fetched externally from locations $BFC0–$BFFF. A switch can be made from this mode to other modes under program control. ...

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... Freescale Semiconductor, Inc. Operating Modes and Memory 2.3 Memory Map Figure 2-1 (single-chip and expanded-multiplexed), as well as for both special modes of operation (bootstrap and test). • In the single-chip mode, the MCU does not generate external addresses. The internal memory locations are shown in the shaded areas, and the contents of these shaded areas are explained on the right side of the diagram ...

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... Freescale Semiconductor, Inc. 2.3.1 Control and Status Registers Figure 2-2 data registers, and reserved locations that make up the internal register block. This block may be mapped to any 4-K boundary in memory, but reset locates it at $0000–$003F. This mappability factor and the default starting addresses are indicated by the use of a bold 0 as the starting character of a register’ ...

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... Freescale Semiconductor, Inc. Operating Modes and Memory Addr. Register Name Timer Compare Force Register $000B (CFORC) See page 104. Reset: Output Compare 1 Mask Register $000C (OC1M) See page 105. Reset: Output Compare 1 Data Register $000D (OC1D) See page 105. Reset: Timer Counter Register High ...

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... Freescale Semiconductor, Inc. Addr. Register Name Timer Output Compare Register 1 $0017 Low (TOC1) See page 103. Reset: Timer Output Compare Register 2 High (TOC2) $0018 See page 103. Reset: Timer Output Compare Register 2 Low (TOC2) $0019 See page 103. Reset: Timer Output Compare Register 3 ...

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... Freescale Semiconductor, Inc. Operating Modes and Memory Addr. Register Name Timer Interrupt Mask 1 Register $0022 (TMSK1) See page 107. Reset: Timer Interrupt Flag 1 Register $0023 (TFLG1) See page 108. Reset: Timer Interrupt Mask 2 Register $0024 (TMSK2) See page 108. Reset: Timer Interrupt Flag 2 Register ...

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... Freescale Semiconductor, Inc. Addr. Register Name SCI Status Register (SCSR) $002E See page 80. Reset: SCI Data Register $002F (SCDR) See page 78. Reset: $0030 Reserved $0038 System Configuration Options $0039 Register (OPTION) See page 53. Reset: Arm/Reset COP Timer Circuitry $003A Register (COPRST) See page 52 ...

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... Freescale Semiconductor, Inc. Operating Modes and Memory 2.3.2 RAM and I/O Mapping Register The random-access memory (RAM) and input/output (I/O) mapping register (INIT special-purpose 8-bit register that is used during initialization to change the default locations of RAM and control registers within the MCU memory map. It can be written to only once within the first 64 E-clock cycles after a reset in normal modes ...

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... Freescale Semiconductor, Inc. normal expanded mode, EPROM is enabled and located at $7000–$7FFF. Should the user wish expanded mode, but with EPROM mapped at $F000–$FFFF, he must reset in single-chip mode, and write the MDA bit in the HPRIO register. Address: $003F ...

Page 32

... Freescale Semiconductor, Inc. Operating Modes and Memory As described in the following subsections, these two methods of programming and verifying EPROM are possible: 1. Programming an individual EPROM address 2. Programming the EPROM with downloaded data 2.4.1 Programming an Individual EPROM Address In this method, the MCU programs its own EPROM by controlling the PPROG register. Use these procedures to program the EPROM through the MCU with: • ...

Page 33

... Freescale Semiconductor, Inc. 2.4.3 PROM Programming Control Register The PROM programming control register (PPROG) is used to control the programming of the OTPROM or EPROM. PPROG is cleared on reset so that the PROM is configured for normal read. Address: $003B Read: Write: Reset: Figure 2-5. PROM Programming Control Register (PPROG) MBE — ...

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... Freescale Semiconductor, Inc. Operating Modes and Memory Data Sheet 34 For More Information On This Product, Operating Modes and Memory Go to: www.freescale.com MC68HC711D3 — Rev. 2 MOTOROLA ...

Page 35

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 3.1 Introduction This section presents information on M68HC11 central processor unit (CPU): • Architecture • Data types • Addressing modes • Instruction set • Special operations such as subroutine calls and interrupts The CPU is designed to treat all peripheral, input/output (I/O), and memory locations identically as addresses in the 64-Kbyte memory map ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 7 ACCUMULATOR CONDITION CODE REGISTER 3.2.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D ...

Page 37

... Freescale Semiconductor, Inc. 3.2.2 Index Register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can also be used as a counter temporary storage register. 3.2.3 Index Register Y (IY) The 16-bit IY register performs an indexed mode function similar to that of the IX register ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) JSR, JUMP TO SUBROUTINE MAIN PROGRAM PC $9D = JSR DIRECT dd RTN NEXT MAIN INSTR MAIN PROGRAM PC $AD = JSR INDXD,X ff RTN NEXT MAIN INSTR MAIN PROGRAM PC $18 = PRE $AD = JSR INDXD,Y ff RTN NEXT MAIN INSTR MAIN PROGRAM PC $BD = JSR ...

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... Freescale Semiconductor, Inc. 3.2.5 Program Counter (PC) The program counter, a 16-bit register, contains the address of the next instruction to be executed. After reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. See Table Mode Normal Test or boot 3 ...

Page 40

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) 3.2.6.4 Negative (N) The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative if its most significant bit (MSB quick way to test whether the contents of a memory location has the MSB set is to load it into an accumulator and then check the status of the N bit ...

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... Freescale Semiconductor, Inc. and processing continues to the next instruction set by reset; STOP is disabled by default. 3.3 Data Types The M68HC11 CPU supports four data types: 1. Bit data 2. 8-bit and 16-bit signed and unsigned integers 3. 16-bit unsigned fractions 4. 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) which the argument is fetched or stored or the address from which execution is to proceed. The effective address can be specified within an instruction can be calculated. 3.5.1 Immediate In the immediate addressing mode, an argument is contained in the byte(s) immediately following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on ...

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... Freescale Semiconductor, Inc. 3.5.6 Relative The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. Otherwise, control proceeds to the next instruction. These are usually 2-byte instructions. ...

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... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description ASLA Arithmetic Shift Left ASLB Arithmetic Shift Left ASLD Arithmetic Shift Left ASR Arithmetic Shift Right b7 b0 ASRA Arithmetic Shift Right A ...

Page 45

... Freescale Semiconductor, Inc. Table 3-2. Instruction Set (Sheet Mnemonic Operation Description BRSET(opr) Branch if Bit(s) ? (M) • (msk) Set (rel) BSET (opr) Set Bit( (msk) BSR (rel) Branch to See Figure 3-2 Subroutine BVC (rel) Branch Overflow Clear BVS (rel) Branch ...

Page 46

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description DAA Decimal Adjust Adjust Sum to BCD A DEC (opr) Decrement M – Memory Byte DECA Decrement A – Accumulator A DECB Decrement B – Accumulator B DES Decrement SP – 1 ...

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... Freescale Semiconductor, Inc. Table 3-2. Instruction Set (Sheet Mnemonic Operation Description LDAB (opr) Load M B Accumulator B LDD (opr) Load Double M A Accumulator D LDS (opr) Load Stack Pointer LDX (opr) Load Index Register X LDY (opr) Load Index Register Y LSL (opr) ...

Page 48

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description ORAA (opr Accumulator A (Inclusive) ORAB (opr Accumulator B (Inclusive) PSHA Push A onto A Stk, – Stack PSHB Push B onto B Stk, – Stack PSHX Push X onto IX Stk, – ...

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... Freescale Semiconductor, Inc. Table 3-2. Instruction Set (Sheet Mnemonic Operation Description SBCB (opr) Subtract with B – M – C Carry from B SEC Set Carry 1 C SEI Set Interrupt 1 I Mask SEV Set Overflow 1 V Flag STAA (opr) Store A M Accumulator A STAB (opr) Store ...

Page 50

... Freescale Semiconductor, Inc. Central Processor Unit (CPU) Table 3-2. Instruction Set (Sheet Mnemonic Operation Description TST (opr) Test for Zero or M – 0 Minus TSTA Test A for Zero A – Minus TSTB Test B for Zero B – Minus TSX Transfer Stack Pointer to X ...

Page 51

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 Section 4. Resets, Interrupts, and Low-Power Modes 4.1 Introduction This section describes the internal and external resets and interrupts of the MC68HC711D3 and its two low power-consumption modes. 4.2 Resets The microcontroller unit (MCU) can be reset in any of these four ways: 1 ...

Page 52

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes 4.2.3 Computer Operating Properly (COP) Reset The MCU contains a watchdog timer that automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, a reset is generated, which drives the RESET pin low to reset the MCU and the external system ...

Page 53

... Freescale Semiconductor, Inc. 4.2.4 Clock Monitor Reset The MCU contains a clock monitor circuit that measures the E-clock frequency. If the E-clock input rate is above approximately 200 kHz, then the clock monitor does not generate an MCU reset. If the E-clock signal is lost or its frequency falls below 10 kHz, then an MCU reset can be generated, and the RESET pin is driven low to reset the external system ...

Page 54

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes CR1 and CR0 — COP Timer Rate Selects The COP system is driven by a constant frequency of E specify an additional divide-by value to arrive at the COP timeout rate. These bits are cleared during reset and can be written only once during the first 64 E-clock cycles after reset in normal modes ...

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... Freescale Semiconductor, Inc. Table 4-2. Interrupt and Reset Vector Assignments (Continued) Vector Address $FFDE, $FFDF $FFE0, $FFE1 $FFE2, $FFE3 $FFE4, $FFE5 $FFE6, $FFE7 $FFE8, $FFE9 $FFEA, $FFEB $FFEC, $FFED $FFEE, $FFEF $FFF0, $FFF1 $FFF2, $FFF3 $FFF4, $FFF5 $FFF6, $FFF7 $FFF8, $FFF9 $FFFA, $FFFB ...

Page 56

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes 4.3.1 Software Interrupt (SWI) The SWI is executed the same as any other instruction and takes precedence over interrupts only if the other interrupts are masked (with I and X bits in the CCR set). SWI execution is similar to that of the maskable interrupts in that it sets the I bit, stacks the central processor unit (CPU) registers, etc ...

Page 57

... Freescale Semiconductor, Inc. 4.3.5 Priority Structure Interrupts obey a fixed hardware priority circuit to resolve simultaneous requests. However one I bit related interrupt source may be elevated to the highest I bit priority in the resolution circuit. Six interrupt sources are not masked by the I bit in the CCR and have these fixed priority relationships: 1 ...

Page 58

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 4-4. Processing Flow Out of Reset (Sheet Data Sheet 58 For More Information On This Product, EXTERNAL RESET ...

Page 59

... Freescale Semiconductor, Inc. STACK CPU REGISTERS SET I BIT FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET I BIT FETCH VECTOR $FFF6, $FFF7 Figure 6-3. Processing Flow Out of Reset (Sheet MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product BIT IN CCR SET? ...

Page 60

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes INTERRUPT RTII = 1 ? OC1I = 1 ? Data Sheet 60 For More Information On This Product, BEGIN X BIT Y XIRQ PIN IN CCR LOW ? SET ? N N HIGHEST Y PRIORITY ? N Y IRQ ? N Y REAL-TIME INTERRUPT ? TIMER IC1I = 1 ? IC1F ? TIMER IC2I = 1 ? IC2F ? ...

Page 61

... Freescale Semiconductor, Inc. 2A OC2I = 1? N OC3I = 1? N OC4I = 1? N OC5I = 1? N TOI = 1? N PAOVI = 1? N PAII = 1? N SPIE = 1? N SCI INTERRUPT? SEE Figure 4-6 N MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product FLAG OC2F = FLAG OC3F = FLAG ...

Page 62

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes BEGIN FLAG RDRF = TDRE = IDLE = VALID SCI REQUEST Data Sheet 62 For More Information On This Product RIE = TIE = ILIE = 1? N Figure 4-6. Interrupt Source Resolution within SCI Resets, Interrupts, and Low-Power Modes Go to: www ...

Page 63

... Freescale Semiconductor, Inc. 4.3.6 Highest Priority I Interrupt and Miscellaneous Register (HPRIO) Four bits of this register (PSEL3–PSEL0) are used to select one of the I bit related interrupt sources and to elevate it to the highest I bit masked position of the priority resolution circuit. In addition, four miscellaneous system control bits are included in this register ...

Page 64

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes IRVNE — Internal Read Visibility/Not E This bit may be read at any time. It may be written once in any mode. IRVNE is set during reset in special test mode only, and cleared by reset in the other modes Data from internal reads is driven out on the external data bus Data from internal reads is not visible on the external data bus ...

Page 65

... Freescale Semiconductor, Inc. 4.4 Low-Power Operation The M68HC11 Family of microcontroller units (MCU) has two programmable low power-consumption modes: stop and wait. In the wait mode, the on-chip oscillator remains active. In the stop mode, the oscillator is stopped. This subsection describes these two low power-consumption modes. ...

Page 66

... Freescale Semiconductor, Inc. Resets, Interrupts, and Low-Power Modes 4.4.2 Wait Mode The wait (WAI) instruction places the MCU in a low power-consumption mode. The wait mode consumes more power than the stop mode since the oscillator is kept running. Upon execution of the WAI instruction, the machine state is stacked and program execution stops ...

Page 67

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 5.1 Introduction The MC68HC711D3 has four 8-bit input/output (I/O) ports and D. In the 40-pin version, port A bits 4 and 6 are not bonded. Port functions are controlled by the particular mode of operation selected, as shown in Functions. In the single-chip and bootstrap modes, all the ports are configured as parallel input/output (I/O) data ports ...

Page 68

... Freescale Semiconductor, Inc. Input/Output (I/O) Ports 5.2 Port A Port A shares functions with the timer system and has: • Three input only pins • Three output only pins • Two bidirectional I/O pins Pins PA6 and PA4 are not bonded in the 40-pin dual in-line package (DIP), and their OC output functions are unavailable, but their software interrupts are available ...

Page 69

... Freescale Semiconductor, Inc. 5.3 Port B Port 8-bit, general-purpose I/O port with a data register (PORTB) and a data direction register (DDRB). • In the single-chip mode, port B pins are general-purpose I/O pins (PB7–PB0). • In the expanded-multiplexed mode, all of the port B pins act as the high-order address bits (A15–A8) of the address bus. ...

Page 70

... Freescale Semiconductor, Inc. Input/Output (I/O) Ports 5.4 Port C Port 8-bit, general-purpose I/O port with a data register (PORTC) and a data direction register (DDRC). In the single-chip mode, port C pins are general-purpose I/O pins (PC7–PC0). In the expanded-multiplexed mode, port C pins are configured as multiplexed address/data pins. During the address cycle, bits 7–0 of the address are output on PC7– ...

Page 71

... Freescale Semiconductor, Inc. 5.4.3 Port C Data Direction Register Address: Read: Write: Reset: DDC7–DDC0 — Data Direction Bits for Port Corresponding port C pin is configured as output 0 = Corresponding port C pin is configured for input only 5.5 Port D Port 8-bit, general-purpose I/O port with a data register (PORTD) and a data direction register (DDRD). The eight port D bits (D7– ...

Page 72

... Freescale Semiconductor, Inc. Input/Output (I/O) Ports 5.5.2 Port D Data Direction Register Address: Read: Write: Reset: DDD7–DDD0 — Data Direction for Port D When port general-purpose I/O port, the DDRD register controls the direction of the I/O pins as follows Configures the corresponding port D pin for input only 1 = Configures the corresponding port D pin for output In expanded and test modes, bits 6 and 7 are dedicated AS and R/W ...

Page 73

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 6.1 Introduction The serial communications interface (SCI universal asynchronous receiver transmitter (UART), one of two independent serial input/output (I/O) subsystems in the MC68HC711D3. It has a standard non-return to zero (NRZ) format (one start, eight or nine data, and one stop bit). Several baud rates are available. The SCI transmitter and receiver are independent, but use the same data format and bit rate ...

Page 74

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TRANSMITTER BAUD RATE SCDR Tx BUFFER CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 6-1. SCI Transmitter Block Diagram Data Sheet 74 For More Information On This Product, ...

Page 75

... Freescale Semiconductor, Inc. 6.4 Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers parallel receive data register (SCDR complete word. Refer to character to be shifted in serially while another character is already in the SCDR. An advanced data recovery scheme distinguishes valid data from noise in the serial data stream ...

Page 76

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 16X BAUD RATE CLOCK DDD0 PIN BUFFER PD0 RxD AND CONTROL DISABLE DRIVER SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 6-2. SCI Receiver Block Diagram Data Sheet 76 For More Information On This Product, ÷16 ...

Page 77

... Freescale Semiconductor, Inc. 6.5.2 Address-Mark Wakeup The serial characters in this type of wakeup consist of seven (eight information bits and an MSB, which indicates an address character (when set to 1 — mark). The first character of each message is an addressing character (MSB = 1). All receivers in the system evaluate this character to determine if the remainder of the message is directed toward this particular receiver ...

Page 78

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 6.7 SCI Registers This subsection describes the five addressable registers in the SCI. 6.7.1 SCI Data Register The SCI data register (SCDR parallel register that performs two functions the receive data register when it is read, and the transmit data register when it is written ...

Page 79

... Freescale Semiconductor, Inc. 6.7.3 SCI Control Register 2 The SCI control register 2 (SCCR2) provides the control bits that enable or disable individual SCI functions. Address: Read: Write: Reset: TIE — Transmit Interrupt Enable Bit 1 = TDRE interrupts disabled 1 = SCI interrupt requested when TDRE status flag is set TCIE — ...

Page 80

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) 6.7.4 SCI Status Register The SCI status register (SCSR) provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. Address: Read: Write: Reset: TDRE — Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and then writing to SCDR ...

Page 81

... Freescale Semiconductor, Inc. NF — Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR with NF set and then reading SCDR Unanimous decision 1 = Noise detected FE — Framing Error Bit FE is set when detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR ...

Page 82

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) SCR2–SCR0 — SCI Baud Rate Select Bits These three bits select receiver and transmitter bit rate based on output from baud rate prescaler stage. SCR2–SCR0 The prescale bits, SCP1 and SCP0, determine the highest baud rate and the SCR2– ...

Page 83

... Freescale Semiconductor, Inc. EXTAL OSCILLATOR AND CLOCK GENERATOR (÷ 4) XTAL 6.8 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be set to enable each of these status conditions to generate interrupt requests when the corresponding condition is present ...

Page 84

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) TDRE and TC flags are normally set when the transmitter is first enabled (TE set to 1). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is the local interrupt mask for TDRE. When TIE is 0, TDRE must be polled ...

Page 85

... Freescale Semiconductor, Inc. BEGIN FLAG RDRF = TDRE = IDLE = VALID SCI REQUEST MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product RIE = TIE = TCIE = ILIE = 1? N Figure 6-9. Interrupt Source Resolution within SCI Serial Communications Interface (SCI) Go to: www ...

Page 86

... Freescale Semiconductor, Inc. Serial Communications Interface (SCI) Data Sheet 86 For More Information On This Product, Serial Communications Interface (SCI) Go to: www.freescale.com MC68HC711D3 — Rev. 2 MOTOROLA ...

Page 87

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 7.1 Introduction The serial peripheral interface (SPI), an independent serial communications subsystem, allows the microcontroller unit (MCU) to communicate synchronously with peripheral devices, such as: • Transistor-transistor logic (TTL) shift registers • Liquid crystal diode (LCD) display drivers • ...

Page 88

... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) PH2 (INTERNAL) DIVIDER ÷2 ÷4 ÷16 ÷32 SPI CLOCK (MASTER) SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST 7.3 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device ...

Page 89

... Freescale Semiconductor, Inc. SCK CYCLE # SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT MSB (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED 7.4 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR) ...

Page 90

... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 7.5 SPI Signals This subsection contains description of the four SPI signals: • Master in/slave out (MISO) • Master out/slave in (MOSI) • Serial clock (SCK) • Slave select (SS) 7.5.1 Master In/Slave Out (MISO) MISO is one of two unidirectional serial data signals input to a master device and an output from a slave device ...

Page 91

... Freescale Semiconductor, Inc. The state of the master and slave CPHA bits affects the operation of SS. CPHA settings should be identical for master and slave. When CPHA = 0, the shift clock is the with SCK. In this clock phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS can be left low between successive SPI characters ...

Page 92

... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) transfer begins when the SCK line goes to its active level, which is the edge at the beginning of the first SCK cycle. The transfer ends in a slave in which CPHA equals one when SPIF is set. For a slave, after a byte transfer, SCK must be in inactive state for at least 2 E-clock cycles before the next byte transfer begins ...

Page 93

... Freescale Semiconductor, Inc. SPR1 and SPR0 — SPI Clock Rate Select Bits These two serial peripheral rate bits select one of four baud rates to be used as SCK if the device is a master; however, they have no effect in the slave mode. 7.7.2 SPI Status Register Address: ...

Page 94

... Freescale Semiconductor, Inc. Serial Peripheral Interface (SPI) 7.7.3 SPI Data I/O Register The SPI data I/O register (SPDR) is used when transmitting or receiving data on the serial bus. Only a write to this register initiates transmission or reception of a byte, and this only occurs in the master device. At the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave devices ...

Page 95

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 8.1 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer's programmable prescaler provides one of the four clocking rates to drive the 16-bit counter. Two prescaler control bits select the prescale rate ...

Page 96

... Freescale Semiconductor, Inc. Programmable Timer OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) PRESCALER (÷ 16, 32) SPR1 AND SPR0 PRESCALER (÷ 13) SCP1 AND SCP0 6 E ÷ ÷ 2 PRESCALER (÷ 16) PR1 AND PR0 TCNT IC/OC Figure 8-1. Timer Clock Divider Chains ...

Page 97

... Freescale Semiconductor, Inc. The COP watchdog clock input (E 2 chain. The COP automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP is allowed to time out, a reset is generated, which drives the RESET pin low to reset the MCU and the external system ...

Page 98

... Freescale Semiconductor, Inc. Programmable Timer MCU E CLOCK PRESCALER — DIVIDE PR1 PR0 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO) 16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK I4/O5 CLK ...

Page 99

... Freescale Semiconductor, Inc. of successive edges of an incoming signal, software can determine the period and pulse width of a signal. To measure period, two successive edges of the same polarity are captured. To measure pulse width, two alternate polarity edges are captured. In most cases, input capture edges are asynchronous to the internal timer counter, which is clocked relative to the PH2 clock ...

Page 100

... Freescale Semiconductor, Inc. Programmable Timer functions only if the I4/O5 bit in PACTL is set. Refer to configuration. 8.3.2 Timer Input Capture Registers When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and timer counter incrementing occur on opposite half-cycles of the phase two clock so that the count value is stable whenever a capture occurs ...

Page 101

... Freescale Semiconductor, Inc. Address: $0013 — TIC2 (Low) Read: Write: Reset: Address: $0014 — TIC3 (High) Read: Write: Reset: Address: $0015 — TIC3 (Low) Read: Write: Reset: Figure 8-4. Timer Input Capture Registers (TICx) (Continued) 8.3.3 Timer Input Capture 4/Output Compare 5 Register Use timer input capture 4/output compare 5 (TI4/O5) as either an input capture register or an output compare register, depending on the function chosen for the I4/O5 pin ...

Page 102

... Freescale Semiconductor, Inc. Programmable Timer 8.4 Output Compare (OC) Use the output compare (OC) function to program an action to occur at a specific time — when the 16-bit counter reaches a specified value. For each of the five output compare functions, there is a separate 16-bit compare register and a dedicated 16-bit comparator. The value in the compare register is compared to the value of the free-running counter on every bus cycle ...

Page 103

... Freescale Semiconductor, Inc. 8.4.1 Timer Output Compare Registers All output compare registers are 16-bit read-write. Each is initialized to $FFFF at reset output compare register is not used for an output compare function, it can be used as a storage location. A write to the high-order byte of an output compare register pair inhibits the output compare function for one bus cycle. This inhibition prevents inappropriate subsequent comparisons ...

Page 104

... Freescale Semiconductor, Inc. Programmable Timer Address: $001B — TOC3 (Low) Read: Write: Reset: Address: $001C — TOC4 (High) Read: Write: Reset: Address: $001D — TOC4 (Low) Read: Write: Reset: Figure 8-6. Timer Output Capture Registers (TOCx) (Continued) 8.4.2 Timer Compare Force Register The timer compare force register (CFORC) allows forced early compares. ...

Page 105

... Freescale Semiconductor, Inc. 8.4.3 Output Compare 1 Mask Register Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA7–PA3. Address: Read: Write: Reset: OC1M7–OC1M3 — Output Compare Masks 0 = OC1 disabled 1 = OC1 enabled to control the corresponding pin of port A Bits 2– ...

Page 106

... Freescale Semiconductor, Inc. Programmable Timer 8.4.5 Timer Counter Register The 16-bit read-only timer count register (TCNT) contains the prescaled value of the 16-bit timer. A full counter read addresses the most significant byte (MSB) first. A read of this address causes the least significant byte (LSB latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit state of the counter at the time of the MSB read cycle ...

Page 107

... Freescale Semiconductor, Inc. 8.4.7 Timer Interrupt Mask 1 Register The timer interrupt mask 1 register (TMSK1 8-bit register used to enable or inhibit the timer input capture and output compare interrupts. Address: Read: Write: Reset: OC1I–OC4I — Output Compare x Interrupt Enable Bits If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested. I4/O5I — ...

Page 108

... Freescale Semiconductor, Inc. Programmable Timer 8.4.8 Timer Interrupt Flag 1 Register The timer interrupt flag 1 register (TFLG1) bits indicate when timer system events have occurred. Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in the same position ...

Page 109

... Freescale Semiconductor, Inc. PAII — Pulse Accumulator Input Edge Interrupt Enable Bit Refer to NOTE: Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. PR1 and PR0 — Timer Prescaler Select Bits These bits are used to select the prescaler divide-by ratio. In normal modes, PR1 and PR0 can be written once only, and the write must be within 64 cycles after reset ...

Page 110

... Freescale Semiconductor, Inc. Programmable Timer 8.5 Real-Time Interrupt The real-time interrupt feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII bit in the TMSK2 register enables the interrupt capability. The four different rates available are a product of the MCU oscillator frequency and the value of bits RTR1 and RTR0 ...

Page 111

... Freescale Semiconductor, Inc. RTII — Real-Time Interrupt Enable Bit 0 = RTIF interrupts disabled 1 = Interrupt requested PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit Refer to PAII — Pulse Accumulator Input Edge Bit Refer to Bits 3–2 — Unimplemented Always read 0. PR1 and PR0 — Timer Prescaler Select Bits ...

Page 112

... Freescale Semiconductor, Inc. Programmable Timer 8.5.3 Pulse Accumulator Control Register Bits RTR1 and RTR0 of the pulse accumulator control register (PACTL) select the rate for the real-time interrupt system. Bit DDRA3 determines whether port A bit three is an input or an output when used for general-purpose I/O. The remaining bits control the pulse accumulator ...

Page 113

... Freescale Semiconductor, Inc. 8.6 Computer Operating Properly Watchdog Function The clocking chain for the COP function, tapped off of the main timer divider chain, is only superficially related to the main timer system. The CR1 and CR0 bits in the OPTION register and the NOCOP bit in the CONFIG register determine the status of the COP function ...

Page 114

... Freescale Semiconductor, Inc. Programmable Timer In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin. The maximum clocking rate for the external event counting mode is the E clock divided by two. In gated time accumulation mode, a free-running E-clock activated. Refer to written at any time. ...

Page 115

... Freescale Semiconductor, Inc. PEDGE — Pulse Accumulator Edge Control Bit This bit has different meanings depending on the state of the PAMOD bit, as shown in DDRA3 — Data Direction Register for Port A Bit 3 Refer to I4/O5 — Input Capture 4/Output Compare 5 Bit Refer to RTR1 and RTR0 — RTI Interrupt Rate Select Bits Refer to 8 ...

Page 116

... Freescale Semiconductor, Inc. Programmable Timer not affect the state of PAOVF. When PAOVI is 0, pulse accumulator overflow interrupts are inhibited, and the system operates in a polled mode, which requires PAOVF to be polled by user software to determine when an overflow has occurred. When the PAOVI control bit is set, a hardware interrupt request is generated each time PAOVF is set ...

Page 117

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 9.1 Introduction This section contains electrical specifications. 9.2 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 9.5 DC Electrical Characteristics ...

Page 118

... Freescale Semiconductor, Inc. Electrical Characteristics 9.3 Functional Operating Temperature Range Rating Operating temperature range MC68HC711D3 MC68HC711D3V 9.4 Thermal Characteristics Characteristic Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 40-pin plastic dual in-line package (DIP) 44-pin plastic leaded chip carrier (PLCC) 44-pin plastic quad flat pack (QFP) ...

Page 119

... Freescale Semiconductor, Inc. 9.5 DC Electrical Characteristics Characteristic (2) Output voltage All outputs I = ± 10.0 µAAll outputs except RESET and MODA Load (1) Output high voltage All outputs except I = – 0.8 mA 4.5 V RESET, EXTAL, and MODA Load DD Output low voltage All outputs except XTAL I = 1.6 mA Load Input high voltage All inputs except RESET ...

Page 120

... Freescale Semiconductor, Inc. Electrical Characteristics Characteristic Input capacitancePA3–PA0, IRQ, XIRQ, EXTAL PA7, PC7–PC0, PD7–PD0, MODA/LIR, RESET Power dissipation Single-chip mode dc — 2 MHz dc — 3 MHz Expanded multiplexed mode dc — 2 MHz dc — 3 MHz EPROM programming voltage EPROM programming time 5.0 Vdc ±10%, V ...

Page 121

... Freescale Semiconductor, Inc CLOCKS, STROBES INPUTS ~ V DD OUTPUTS ~ TESTING ~ V DD CLOCKS, STROBES INPUTS ~ V DD OUTPUTS ~ TESTING Note: 1. During ac timing measurements, inputs are driven to 0.4 volts and V at the 20% and 70 points. DD MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product ...

Page 122

... Freescale Semiconductor, Inc. Electrical Characteristics 9.6 Control Timing Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup timet = 1/4 t PCSU (2) Reset input pulse width To guarantee external reset vector Minimum input time can be preempted by internal reset Mode programming setup time ...

Page 123

... Freescale Semiconductor, Inc ...

Page 124

... Freescale Semiconductor, Inc. Electrical Characteristics ...

Page 125

... Freescale Semiconductor, Inc. MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product, Electrical Characteristics Go to: www.freescale.com Electrical Characteristics Control Timing Data Sheet 125 ...

Page 126

... Freescale Semiconductor, Inc. Electrical Characteristics Data Sheet 126 For More Information On This Product, Electrical Characteristics Go to: www.freescale.com MC68HC711D3 — Rev. 2 MOTOROLA ...

Page 127

... Freescale Semiconductor, Inc. 9.7 Peripheral Port Timing (1) Characteristic Frequency of operation (E-clock frequency) E-clock period (2) Peripheral data setup time MCU read of ports and D (2) Peripheral data hold time MCU read of ports and D Delay time, peripheral data write MCU write to port A MCU writes to ports B, C, and D ...

Page 128

... Freescale Semiconductor, Inc. Electrical Characteristics 9.8 Expansion Bus Timing Num Characteristic Frequency of operation (E-clock frequency) 1 Cycle time Pulse width, E low 1 Pulse width, E high 1 and AS rise time 4B E and AS fall time (2)a 9 Address hold time , Non-muxed address valid time to E rise ...

Page 129

... Freescale Semiconductor, Inc. E R/W, ADDRESS (NON-MUX) 36 READ ADDRESS/DATA (MULTIPLEXED) WRITE Note: Measurement points shown are 20% and 70 Figure 9-10. Multiplexed Expansion Bus Timing Diagram MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product ADDRESS 19 ADDRESS Electrical Characteristics Go to: www ...

Page 130

... Freescale Semiconductor, Inc. Electrical Characteristics 9.9 Serial Peripheral Interface Timing Num Characteristic Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time (2) 2 Master Slave Enable lag time (2) 3 Master Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low time ...

Page 131

... Freescale Semiconductor, Inc. SS (INPUT) SCK (CPOL = 0) SEE NOTE (OUTPUT) SCK (CPOL = 1) SEE NOTE (OUTPUT) MISO (INPUT) 10 (REF) MOSI (OUTPUT) Note: This first clock edge is generated internally but is not seen at the SCK pin. Figure 9-11. SPI Master Timing (CPHA = 0) SS (INPUT) SCK (CPOL = 0) ...

Page 132

... Freescale Semiconductor, Inc. Electrical Characteristics SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 MISO SLAVE (OUTPUT) 6 MOSI (INPUT) Note: Not defined but normally MSB of character just received Figure 9-13. SPI Slave Timing (CPHA = 0) SS (INPUT) SCK (CPOL = 0) (INPUT) 2 SCK (CPOL = 1) (INPUT) 8 SEE MISO ...

Page 133

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 Section 10. Ordering Information and Mechanical Specifications 10.1 Introduction This section provides ordering information for the MC68HC711D3. In addition, mechanical specifications are provided for the following packaging options: • 40-pin plastic dual in-line package (DIP) • 44-pin plastic leaded chip carrier (PLCC) • ...

Page 134

... Freescale Semiconductor, Inc. Ordering Information and Mechanical Specifications 10.3 40-Pin DIP (Case 711-03 Data Sheet 134 Ordering Information and Mechanical Specifications For More Information On This Product SEATING PLANE Go to: www.freescale.com NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0 ...

Page 135

... Freescale Semiconductor, Inc. 10.4 44-Pin PLCC (Case 777-02) -N- - ...

Page 136

... Freescale Semiconductor, Inc. Ordering Information and Mechanical Specifications 10.5 44-Pin QFP (Case 824A-01 - -D- A 0.20 (0.008) M 0.05 (0.002) A-B S 0.20 (0.008 -C- H SEATING G PLANE DATUM -H- PLANE W DETAIL C Data Sheet 136 Ordering Information and Mechanical Specifications For More Information On This Product -B- DETAIL A ...

Page 137

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 A.1 Introduction The MC68HC11D3 and MC68HC11D0 are read-only memory (ROM) based high-performance microcontrollers (MCU) based on the MC68HC11E9 design. Members of the Dx series are derived from the same mask and feature a high-speed multiplexed bus capable of running MHz and a fully static design that allows operations at frequencies to dc ...

Page 138

... Freescale Semiconductor, Inc. MC68HC11D3 and MC68HC11D0 A.2 Block Diagram MODA/LIR RESET MODB/V STBY MODE CONTROL PA7 PA6 PA5 PA4 PORT A PA3 PA2 PA1 PA0 MULTIPLEXED ADDRESS/DATA BUS DATA DIRECTION REGISTER B PORT B Figure A-1. MC68HC11D3 Block Diagram Data Sheet 138 For More Information On This Product, ...

Page 139

... Freescale Semiconductor, Inc. A.3 Pin Assignments MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product, 7 PC4/A4/D4 8 PC5/A5/D5 9 PC6/A6/D6 10 PC7/A7/D7 11 XIRQ 12 PD7/R/W 13 PD6/AS 14 RESET 15 IRQ PD0/RxD 16 17 PD1/TxD Figure A-2. Pin Assignments for 44-Pin PLCC PC4 1 PC5 2 PC6 3 4 PC7 5 XIRQ 6 PD7 7 PD6 8 RESET ...

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... Freescale Semiconductor, Inc. MC68HC11D3 and MC68HC11D0 A.4 Memory Map $0000 $7000 $8000 EXTERNAL $B000 $FFFF SINGLE EXPANDED CHIP MULTIPLEXED BOOTSTRAP Figure A-4. MC68HC11Dx A.5 MC68HC11D3 and MC68HC11D0 Electrical Characteristics The parameters given in MC68HC11D3 and MC68HC11D0 with the exceptions given here. A.5.1 Functional Operating Temperature Range ...

Page 141

... ROM) MC68HC711D3 — Rev. 2 MOTOROLA For More Information On This Product, Package Temperature 44-pin PLCC –40 to +85 C MC68HC11D3CFN2 44-pin PLCC –40 to +85 C MC68HC11D0CFN2 44-pin QFP –40 to +85 C MC68HC11D0CFB2 MC68HC11D3 and MC68HC11D0 Go to: www.freescale.com MC68HC11D3 and MC68HC11D0 MC Order Number 2 MHz 3 MHz MC68HC11D3CFN3 ...

Page 142

... Freescale Semiconductor, Inc. MC68HC11D3 and MC68HC11D0 Data Sheet 142 For More Information On This Product, MC68HC11D3 and MC68HC11D0 Go to: www.freescale.com MC68HC711D3 — Rev. 2 MOTOROLA ...

Page 143

... Freescale Semiconductor, Inc. Data Sheet — MC68HC711D3 B.1 Introduction The MC68L11D0 is an extended-voltage version of the MC68HC11D0 microcontroller that can operate in applications that require supply voltages as low as 3.0 volts. Operation is identical to that of the MC68HC11D0 (see MC68HC11D3 and as shown in this appendix. Features of the MC68HC11D0 include: • ...

Page 144

... Freescale Semiconductor, Inc. MC68L11D0 Characteristic Input high voltage RESET Input low voltage All inputs I/O ports, three-state leakage Input leakage current RAM standby voltage RAM standby current Input capacitance PA3, PA7, PC7–PC0, PD7–PD0, MODA/LIR, RESET ...

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... Freescale Semiconductor, Inc. B.2.3 Control Timing Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time PCSU cyc (2) Reset input pulse width To guarantee external reset vector Minimum input time can be preempted by internal reset Interrupt pulse width, PW ...

Page 146

... Freescale Semiconductor, Inc. MC68L11D0 B.2.5 Expansion Bus Timing Num Characteristic Frequency of operation (E-clock frequency) 1 Cycle time Pulse width, E low 1 Pulse width, E high 1 and AS rise time 4B E and AS fall time (2)a 9 Address hold time , Non-muxed address valid time to E rise ...

Page 147

... Freescale Semiconductor, Inc. B.2.6 Serial Peripheral Interface Timing Num Characteristic Operating frequency Master Slave Cycle time 1 Master Slave Enable lead time (2) 2 Master Slave Enable lag time (2) 3 Master Slave Clock (SCK) high time 4 Master Slave Clock (SCK) low time 5 Master Slave ...

Page 148

... Freescale Semiconductor, Inc. MC68L11D0 B.3 Ordering Information Package 44-pin PLCC 44-pin QFP Data Sheet 148 For More Information On This Product, Frequency Features 2 MHz No ROM 2 MHz No ROM MC68L11D0 Go to: www.freescale.com MC Order Number MC68L11D0FN2 MC68L11D0FB2 MC68HC711D3 — Rev. 2 MOTOROLA ...

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... Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com ...

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... Freescale Semiconductor, Inc. HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N ...

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