mc68hc705j2 Freescale Semiconductor, Inc, mc68hc705j2 Datasheet - Page 78

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mc68hc705j2

Manufacturer Part Number
mc68hc705j2
Description
8-bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC705J2
NOTES:
INTERNA
INTERNA
ADDRESS
INTERNA
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
3. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
OSC1 PIN
NOTES:
INTERNA
INTERNA
ADDRESS
INTERNA
CLOCK
RESET
1. Internal clock, internal address bus, and internal data bus signals are not available externally.
2. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
3. Address of high byte of reset vector is $0FFE in MC68HC705J2 native mode and $07FE in MC68HC05J1 emulation mode.
4. Address of low byte of reset vector is $0FFF in MC68HC705J2 native mode and $07FF in MC68HC05J1 emulation mode.
DATA
CLOCK
BUS
BUS
DATA
BUS
BUS
V DD
1
1
1
2
1
1
1
t VDDR
POR THRESHOLD (TYPICALLY
Figure 10-8. Power-On Reset Timing
0FFE 3
t RL
Figure 10-9. External Reset Timing
ELECTRICAL SPECIFICATIONS
0FFE
0FFE
2
3
0FFE
0FFE
2
3
4064 cyc
0FFE
0FFE
2
NEW
PCH
3
0FFE
0FFF
2
NEW
PCL
4
0FFE
NEW PC
DUMMY
2
0FFE
NEW
PCH
NEW PC
2
CODE
OP
0FFF
NEW
PCL
MOTOROLA
3
10-11

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