mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 103

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
10.4.1 Slave Select (SS/PB0)
MC68HC705V12
NOTE:
Rev. 3.0
The slave select (SS) pin is used to select the MCU as a slave device. It
has to be low prior to data transactions and must stay low for the duration
of the transaction. The SS pin on the master must be set high. If it goes
low, a mode fault error flag (MODF) is set in the SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS pin
could be set low as long as CPHA = 1 clock modes are used.
If the SPI is in master mode, this pin can be used as a general-purpose
output pin. If configured as an input pin while in master mode, it must be
set high.
MISO/MOSI
(CPOL = 0,
(CPOL = 0,
(CPOL = 1,
(CPOL = 1,
CPHA = 0)
CPHA = 1)
CPHA = 0)
CPHA = 1)
Freescale Semiconductor, Inc.
SCK
SCK
SCK
SCK
For More Information On This Product,
SS
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
MSB
Figure 10-1. Data Clock Timing Diagram
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
6
5
4
3
Serial Peripheral Interface (SPI)
2
SPI Signal Description
Advance Information
1
0

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