mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 156

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Controller – Digital (BDLC–D)
Advance Information
Valid EOF and IFS Symbols
Idle Bus
ACTIVE
PASSIVE
ACTIVE
PASSIVE
In
beginning the SOF symbol of the next message occurs between a
and b, the current symbol will be considered a valid end-of-frame
(EOF) symbol.
See
beginning the SOF symbol of the next message occurs between c
and d, the current symbol will be considered a valid EOF symbol
followed by a valid inter-frame separation symbol (IFS). All nodes
must wait until a valid IFS symbol time has expired before beginning
transmission. However, due to variations in clock frequencies and bus
loading, some nodes may recognize a valid IFS symbol before others
and immediately begin transmitting. Therefore, any time a node
waiting to transmit detects a passive-to-active transition once a valid
EOF has been detected, it should immediately begin transmission,
initiating the arbitration process.
In
beginning the start-of-frame (SOF) symbol of the next message does
not occur before d, the bus is considered to be idle, and any node
wanting to transmit a message may do so immediately.
Freescale Semiconductor, Inc.
For More Information On This Product,
Byte Data Link Controller – Digital (BDLC–D)
Figure
Figure
Figure
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14-9(1), if the passive-to-active received transition
14-9(2), if the passive-to-active received transition
Figure 14-9. J1850 VPW Received Passive
14-9(2). If the passive-to-active received transition
280 s
EOF and IFS Symbol Times
300 s
a
b
c
MC68HC705V12
d
(1) VALID EOF SYMBOL
(2) VALID EOF+
IFS SYMBOL
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Rev. 3.0