mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 157

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC705V12
Rev. 3.0
Invalid Active Bit
Valid Active Logic 1
Valid Active Logic 0
PASSIVE
PASSIVE
PASSIVE
PASSIVE
In
beginning the next data bit (or symbol) occurs between the
passive-to-active transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
In
beginning the next data bit (or symbol) occurs between a and b, the
current bit would be considered a logic 1.
In
beginning the next data bit (or symbol) occurs between b and c, the
current bit would be considered a logic 0.
Freescale Semiconductor, Inc.
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
Figure
Figure
Figure
Figure 14-10. J1850 VPW Received Active Symbol Times
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14-10(1), if the active-to-passive received transition
14-10(2), if the active-to-passive received transition
14-10(3), if the active-to-passive received transition
64 s
a
a
128 s
200 s
b
b
Byte Data Link Controller – Digital (BDLC–D)
c
c
d
(1) INVALID ACTIVE BIT
(2) VALID ACTIVE LOGIC 1
(3) VALID ACTIVE LOGIC 0
(4) VALID SOF SYMBOL
BDLC MUX Interface
Advance Information

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