mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 158

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Byte Data Link Controller – Digital (BDLC–D)
14.5.5 Message Arbitration
Advance Information
Valid SOF Symbol
Valid BREAK Symbol
Message arbitration on the J1850 bus is accomplished in a
non-destructive manner, allowing the message with the highest priority
to be transmitted, while any transmitters which lose arbitration simply
stop transmitting and wait for an idle bus to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that
another message is in progress, it waits until the bus is idle. However, if
multiple nodes begin to transmit in the same synchronization window,
message arbitration will occur beginning with the first bit after the SOF
symbol and continue with each bit thereafter. If a write to the BDR (for
instance, to initiate transmission) occurred on or before
104 • t
ACTIVE
PASSIVE
In
beginning the next data bit (or symbol) occurs between c and d, the
current symbol would be considered a valid SOF symbol.
In
not occur until after e, the current symbol will be considered a valid
BREAK symbol. A BREAK symbol should be followed by a
start-of-frame (SOF) symbol beginning the next message to be
transmitted onto the J1850 bus. See
BDLC response to BREAK symbols.
Freescale Semiconductor, Inc.
Figure 14-11. J1850 VPW Received BREAK Symbol Times
For More Information On This Product,
Byte Data Link Controller – Digital (BDLC–D)
Figure
Figure
BDLC
from the received rising edge, then the BDLC will transmit
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14-11, if the next active-to-passive received transition does
14-10(4), if the active-to-passive received transition
240 s
14.5.2 J1850 Frame Format
e
MC68HC705V12
(2) VALID BREAK
SYMBOL
—
Rev. 3.0
for