mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 167

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
14.7.1 BDLC Analog and Roundtrip Delay
MC68HC705V12
NOTE:
Rev. 3.0
Address:
This register programs the BDLC to compensate for various delays of
different external transceivers. The default delay value is 16 s. Timing
adjustments from 9 s to 24 s in steps of 1 s are available. The BARD
register can be written only once after each reset, after which they
become read-only bits. The register may be read at any time.
ATE — Analog Transceiver Enable Bit
This device does not contain an on-board transceiver. This bit should be
programmed to a logic 0 for proper operation.
RXPOL — Receive Pin Polarity Bit
Reset:
Read:
Write:
The analog transceiver enable (ATE) bit is used to select either the
on-board or an off-chip analog transceiver.
The receive pin polarity (RXPOL) bit is used to select the polarity of
an incoming signal on the receive pin. Some external analog
transceivers invert the receive signal from the J1850 bus before
feeding it back to the digital receive pin.
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
1 = Select on-board analog transceiver
0 = Select off-chip analog transceiver
1 = Select normal/true polarity; true non-inverted signal from the
0 = Select inverted polarity, where an external transceiver inverts
$003E
Bit 7
ATE
J1850 bus; for example, the external transceiver does not
invert the receive signal
the receive signal from the J1850 bus
1
Figure 14-16. BDLC Analog and Roundtrip
Go to: www.freescale.com
= Unimplemented
RXPOL
6
1
Delay Register (BARD)
5
0
0
Byte Data Link Controller – Digital (BDLC–D)
4
0
0
BO3
3
0
BO2
2
1
BDLC CPU Interface
Advance Information
BO1
1
1
Bit 0
BO0
1

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