mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 171

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

14.7.3 BDLC Control Register 2
MC68HC705V12
—
Rev. 3.0
Address:
WCM — Wait Clock Mode Bit
This register controls transmitter operations of the BDLC. It is
recommended that BSET and BCLR instructions be used to manipulate
data in this register to ensure that the register’s content does not change
inadvertently.
ALOOP — Analog Loopback Mode Bit
Reset:
Read:
Write:
This bit determines the operation of the BDLC during CPU wait mode.
See
use.
This bit determines whether the J1850 bus will be driven by the
analog physical interface’s final drive stage. The programmer can use
this bit to reset the BDLC state machine to a known state after the
off-chip analog transceiver is placed in loopback mode. When the
user clears ALOOP, to indicate that the off-chip analog transceiver is
no longer in loopback mode, the BDLC waits for an EOF symbol
before attempting to transmit. Most transceivers have the ALOOP
feature available.
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
1 = Input to the analog physical interface’s final drive stage is
0 = The J1850 bus will be driven by the BDLC. After the bit is
14.8.2 Stop Mode
ALOOP
$003B
Bit 7
looped back to the BDLC receiver. The J1850 bus is not
driven.
cleared, the BDLC requires the bus to be idle for a minimum of
end-of-frame symbol time (t
1
Figure 14-18. BDLC Control Register 2 (BCR2)
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DLOOP
6
1
RX4XE
5
0
and
14.8.1 Wait Mode
NBFS
Byte Data Link Controller – Digital (BDLC–D)
4
0
TRV4
TEOD
) before message reception or
3
0
TSIFR
for more details on its
2
0
BDLC CPU Interface
Advance Information
TMIFR1
1
0
TMIFR0
Bit 0
0