mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 177

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC705V12
NOTE:
Rev. 3.0
The extra logic 1s are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise
on the J1850 bus from corrupting a message.
TMIFR0 — Transmit Multiple Byte IFR without CRC (Type 3) Bit
However, if the programmer wishes to transmit a single byte followed
by a CRC byte, the programmer should load the byte into the BDR
before the EOD symbol has been received, and then set the TMIFR1
bit. Once the TDRE interrupt occurs, the programmer should then set
the TEOD bit in the BCR2. This will result in the byte in the BDR being
the only byte transmitted before the IFR CRC byte, and no TDRE
interrupt will be generated.
If the programmer attempts to set the TMIFR1 bit immediately after
the EOD symbol has been received from the bus, the TMIFR1 bit will
remain in the reset state, and no attempt will be made to transmit an
IFR byte.
If a loss of arbitration occurs when the BDLC is transmitting any byte
of a multiple byte IFR, the BDLC will go to the loss of arbitration state,
set the appropriate flag, and cease transmission.
If the BDLC loses arbitration during the IFR, the TMIFR1 bit will be
cleared and no attempt will be made to retransmit the byte in the
BDR. If loss of arbitration occurs in the last two bits of the IFR byte,
two additional 1 bits will be sent out.
The TMIFR0 bit is used to request the BDLC to transmit the byte in
the BDLC data register (BDR) as the first byte of a multiple byte IFR
without CRC. Response IFR bytes are still subject to J1850 message
length maximums (see
14-19.
Freescale Semiconductor, Inc.
Byte Data Link Controller – Digital (BDLC–D)
For More Information On This Product,
1 = If this bit is set prior to a valid EOD being received with no CRC
error, once the EOD symbol has been received, the BDLC will
attempt to transmit the appropriate normalization bit followed
by IFR bytes. The programmer should set TEOD after the last
IFR byte has been written into the BDR. After TEOD has been
set, the last IFR byte to be transmitted will be the last byte
which was written into the BDR.
Go to: www.freescale.com
14.5.2 J1850 Frame
Byte Data Link Controller – Digital (BDLC–D)
Format). See
BDLC CPU Interface
Advance Information
Figure

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