mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 56

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

Interrupts
4.2 Introduction
4.3 CPU Interrupt Processing
Advance Information
The MCU can be interrupted eight different ways:
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
reset, hardware interrupts do not cause the current instruction execution
to be halted, but are considered pending until the current instruction is
complete.
If interrupts are not masked (I bit in the condition code register (CCR) is
clear) and the corresponding interrupt enable bit is set, then the
processor will proceed with interrupt processing. Otherwise, the next
instruction is fetched and executed. If an interrupt occurs, the processor
completes the current instruction, then stacks the current CPU register
states, sets the I bit to inhibit further interrupts, and finally checks the
pending hardware interrupts. If more than one interrupt is pending after
the stacking operation, the interrupt with the highest vector location
shown in
as any other instruction, regardless of the I-bit state.
When an interrupt is to be processed, the central processor unit (CPU)
fetches the address of the appropriate interrupt software service routine
from the vector table at locations $3FF0–$3FFF as defined in
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. External interrupt via IRQ on PC0–PC7 (IRQ)
4. Internal 16-bit timer interrupt (TIMER)
5. Internal BDLC interrupt (BDLC)
6. Internal serial peripheral interface interrupt (SPI)
7. Internal 8-bit timer interrupt (CTIMER)
8. Internal gauge interrupt (GAUGE)
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-1
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will be serviced first. The SWI is executed the same
Interrupts
MC68HC705V12
Table
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Rev. 3.0
4-1.