mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 62
mc68hc705v12
Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC705V12.pdf
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Interrupts
4.7.1 IRQ Status and Control Register
Advance Information
NOTE:
Address:
these features permit the safe use of read-modify-write instructions (for
instance, BSET and BCLR) on the ISCR.
Although read-modify-write instruction use is allowable on the ISCR,
shift operations should be avoided due to the possibility of inadvertently
setting the IRQA.
The IRQ interrupt function is controlled by the IRQ status and control
register (ISCR) located at $001F. All unused bits in the ISCR will read as
logic 0s. The IRQF bit is cleared and IRQE bit is set by reset.
IRQE — IRQ Interrupt Enable Bit
IPCE — Port C IRQ Interrupt Enable Bit
Reset:
Read:
Write:
The IRQE bit controls whether the IRQF flag bit can or cannot initiate
an IRQ interrupt sequence. If the IRQE enable bit is set, the IRQF flag
bit can generate an interrupt sequence. If the IRQE enable bit is
cleared, the IRQF flag bit cannot generate an interrupt sequence.
Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once
the I bit is cleared. Execution of the STOP or WAIT instructions
causes the IRQE bit to be set to allow the external IRQ to exit these
modes. In addition, reset also sets the I bit, which masks all interrupt
sources.
The IPCE bit controls whether the IPCF flag bit can or cannot initiate
an IRQ interrupt sequence. If the IPCE enable bit is set, the IPCF flag
bit will generate an interrupt sequence. If the IPCE enable bit is
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-3. IRQ Status and Control Register (ISCR)
$001F
IRQE
Bit 7
1
Go to: www.freescale.com
= Unimplemented
6
0
0
Interrupts
IPCE
5
0
4
0
0
IRQF
3
0
MC68HC705V12
2
0
0
IPCF
1
0
—
Rev. 3.0
IRQA
Bit 0
0
0
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