mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 79

• Manufacturer Part Number: mc68hc705v12
• Description: M68hc05-based Mcu Hc05 Freescale Semiconductor
• Manufacturer: Freescale Semiconductor, Inc

6.5 WAIT Instruction
6.6 Data-Retention Mode
MC68HC705V12
NOTE:
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Rev. 3.0
The WAIT instruction places the MCU in a low-power mode, which
consumes more power than stop mode. In wait mode, the internal
processor clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be
generated from the timer or a reset to be generated from the COP
watchdog timer. Execution of the WAIT instruction automatically clears
the I bit in the condition code register. All other registers, memory, and
input/output lines remain in their previous states.
If timer interrupts are enabled, a timer interrupt will cause the processor
to exit wait mode and resume normal operation. The timer may be used
to generate a periodic exit from wait mode.
The MCU can be brought out of wait mode by:
Contents of the random-access memory (RAM) and central processor
unit (CPU) registers are retained at supply voltages as low as 2.0 Vdc.
This is called the data-retention mode where the data is held, but the
device is not guaranteed to operate. The RESET pin must be held low
during data-retention mode.
More power is consumed in data-retention mode than in stop mode
because internal clocks remain running.
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Freescale Semiconductor, Inc.
For More Information On This Product,
A TIMER interrupt from either timer
A serial peripheral interface (SPI) interrupt
An IRQ pin external interrupt
An externally generated reset
A falling edge on any port C pin, if enabled
A rising edge on the BDLC RXP pin
A gauge sequence interrupt
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Low-Power Modes
Advance Information
Low-Power Modes
WAIT Instruction