mc68hc705v12 Freescale Semiconductor, Inc, mc68hc705v12 Datasheet - Page 91

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mc68hc705v12

Manufacturer Part Number
mc68hc705v12
Description
M68hc05-based Mcu Hc05 Freescale Semiconductor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.4 Computer Operating Properly (COP) Reset
MC68HC705V12
Rev. 3.0
The computer operating properly (COP) watchdog timer function is
implemented on this device by using the output of the RTI circuit and
further dividing it by eight. The minimum COP reset rates are listed in
Figure
and the normal reset vector is fetched. Preventing a COP timeout, or
clearing the COP, is accomplished by writing a 0 to bit 0 of address
$3FF0. When the COP is cleared, only the final divide-by-eight stage
(output of the RTI) is cleared. The COP time out period will vary
depending on when the COP is fed with respect to the RTI output clock.
If the COP watchdog timer is allowed to time out, an internal reset is
generated to reset the MCU. In addition the RESET pin will be pulled low
for a minimum of three E clock cycles for emulation purposes. During a
chip reset (regardless of the source), the entire core timer counter chain
is cleared.
The COP will remain enabled after execution of the WAIT instruction and
all associated operations apply. If the STOP instruction is disabled,
execution of STOP instruction will cause an internal reset.
This COP’s objective is to make it impossible for this part to become
“stuck” or “locked-up” and to be sure the COP is able to “rescue” the part
from any situation where it might entrap itself in an abnormal or
unintended behavior. This function is a mask option.
Freescale Semiconductor, Inc.
For More Information On This Product,
8-1. If the COP circuit times out, an internal reset is generated
Go to: www.freescale.com
Core Timer
Computer Operating Properly (COP) Reset
Advance Information
Core Timer

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