mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 119

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

8.6.2 PLL Bandwidth Control Register
MC68HC708MP16
Freescale Semiconductor
—
Rev. 3.1
Address:
The PLL bandwidth control register does the following:
AUTO — Automatic Bandwidth Control Bit
LOCK — Lock Indicator Bit
Reset:
Read:
Write:
•
•
•
•
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode.
Figure 8-6. PLL Bandwidth Control Register (PBWC)
$FE0C
AUTO
Bit 7
0
Clock Generator Module (CGM)
= Unimplemented
LOCK
6
0
ACQ
0
5
XLD
0
4
3
0
0
Clock Generator Module (CGM)
2
0
0
1
0
0
Technical Data
Bit 0
0
0
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