mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 128

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
Technical Data
128
The K factor in the equations is derived from internal PLL parameters.
K
K
8.4.2.2 Acquisition and Tracking
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
Manual and Automatic PLL Bandwidth
clock cycles, n
tracking mode entry tolerance, ∆
certain number of clock cycles, n
PLL is within the lock mode entry tolerance, ∆
acquisition time, t
acquisition to lock time, t
since the average frequency over the entire measurement period must
be within the specified tolerance, the total time usually is longer than
t
In manual mode, it is usually necessary to wait considerably longer than
t
Circuit) because the factors described in
on Reaction Time
LOCK
LOCK
ACQ
TRK
is the K factor when the PLL is configured in tracking mode. (See
is the K factor when the PLL is configured in acquisition mode, and
as calculated above.
before selecting the PLL clock (see
Clock Generator Module (CGM)
ACQ
ACQ
, is required to ascertain that the PLL is within the
may slow the lock time considerably.
, is an integer multiple of n
t
ACQ
t
AL
AL
t
LOCK
, is an integer multiple of n
=
=




TRK
=
V
----------- -
TRK
f
V
----------- -
f
RDV
RDV
DDA
Modes.)
DDA
t
, before exiting acquisition mode. A
ACQ
, is required to ascertain that the








+
---------- -
K
8.10.2 Parametric Influences
----------- -
K
Modes.) A certain number of
8.4.3 Base Clock Selector
4
TRK
t
ACQ
8
AL
LOCK


MC68HC708MP16


ACQ
Freescale Semiconductor
. Therefore, the
/f
RDV
TRK
, and the
/f
RDV
8.4.2.3
. Also,
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Rev. 3.1