mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 163

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mc68hc708mp16

Manufacturer Part Number
mc68hc708mp16
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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mc68hc708mp16CFU
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MC68HC708MP16
Freescale Semiconductor
Rev. 3.1
Address:
To allow for different motor configurations and the controlling of more
than one motor, the PWM disabling function is organized as two banks,
bank X and bank Y. Bank information combines with information from
the disable mapping register to allow selective PWM disabling. Fault pin
1, fault pin 2, and PWM disable bit X constitute the disabling function of
bank X. Fault pin 3, fault pin 4, and PWM disable bit Y constitute the
disabling function of bank Y.
disable mapping write-once register and the decoding scheme of the
bank which selectively disables PWM(s). When all bits of the disable
mapping register are set, any disable condition will disable all PWMs.
A fault can also generate a CPU interrupt. Each fault pin has its own
interrupt vector.
Reset:
Read:
Write:
Pulse Width Modulator for Motor Control (PWMMC)
$0037
BIT 7
Bit 7
1
Figure 9-33. PWM Disable Mapping
BIT 6
6
1
Write-Once Register (DISMAP)
BIT 5
5
1
Pulse Width Modulator for Motor Control (PWMMC)
Figure 9-33
BIT 4
4
1
BIT 3
and
3
1
Figure 9-34
BIT 2
2
1
BIT 1
1
1
show the
Technical Data
BIT 0
Bit 0
1
163

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