mc68hc708mp16 Freescale Semiconductor, Inc, mc68hc708mp16 Datasheet - Page 210

• Manufacturer Part Number: mc68hc708mp16
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module A (TIMA)
11.4.4.2 Buffered PWM Signal Generation
11.4.4.3 PWM Initialization
Technical Data
210
NOTE:
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTE1/TCH0A pin. The TIMA channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMA channel 0 status and control register
(TASC0) links channel 0 and channel 1. The TIMA channel 0 registers
initially control the pulse width on the PTE1/TCH0A pin. Writing to the
TIMA channel 1 registers enables the TIMA channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMA channel registers (0 or
1) that control the pulse width are the ones written to last. TASC0
controls and monitors the buffered PWM function, and TIMA channel 1
status and control register (TASC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTE2/TCH1A, is available as a general-purpose
I/O pin.
In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIMA status and control register (TASC):
2. In the TIMA counter modulo registers (TAMODH:TAMODL), write
3. In the TIMA channel x registers (TACHxH:TACHxL), write the
a. Stop the TIMA counter by setting the TIMA stop bit, TSTOP.
b. Reset the TIMA counter by setting the TIMA reset bit, TRST.
the value for the required PWM period.
value for the required pulse width.
Timer Interface Module A (TIMA)
MC68HC708MP16
Freescale Semiconductor
—
Rev. 3.1